OV - attention-clang-znver5-256 - Loop 52 - attention-clang-znver5-256

	Loop Id: 52	Module: attention-clang-znver5-256	Source: attention_v2.cpp:26-33	Coverage: 0.68%

0x6aa9 MOV	0x40(%RSP),%R11

0x6aae MOV	0x30(%RSP),%R15

0x6ab3 MOV	0x170(%RSP),%RCX

0x6abb MOV	0x1b0(%RSP),%RDX

0x6ac3 MOV	0x38(%RSP),%RSI

0x6ac8 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x6acc MOV	%R11,%R13

0x6acf ADD	%R15D,%ECX

0x6ad2 INC	%R15

0x6ad5 VMOVSS	%XMM0,(%RDX,%RCX,4)

0x6ada CMP	0x28(%RSP),%R15

0x6adf JE	6a5d

0x6ae5 VXORPS	%XMM0,%XMM0,%XMM0

0x6ae9 MOV	%R15,0x30(%RSP)

0x6aee CMP	$0x4,%R13D

0x6af2 JB	6b0e

0x6af4 MOV	%R15D,%ECX

0x6af7 ADD	0x2f8(%RSP),%ECX

0x6afe SETB	%CL

0x6b01 OR	0xe0(%RSP),%CL

0x6b08 JE	6d46

0x6b0e XOR	%ECX,%ECX

0x6b10 MOV	0x58(%RSP),%RDX

0x6b15 SUB	%ECX,%EDX

0x6b17 AND	$0x7,%EDX

0x6b1a JE	6b6c

0x6b1c MOV	0x38(%RSP),%R9

0x6b21 MOV	0x40(%RSP),%R11

0x6b26 MOV	0x88(%RSP),%R14

0x6b2e MOV	%RCX,%R8

0x6b31 MOV	%R9,%RSI

0x6b34 IMUL	%RCX,%RSI

0x6b38 ADD	0x30(%RSP),%RSI

0x6b3d NOPL	(%RAX)

  (54) 0x6b40 LEA	(%RAX,%R8,1),%EDI

  (54) 0x6b44 INC	%R8

  (54) 0x6b47 VMOVSS	(%R12,%RDI,4),%XMM1

  (54) 0x6b4d MOV	%ESI,%EDI

  (54) 0x6b4f VMOVSS	(%R14,%RDI,4),%XMM2

  (54) 0x6b55 ADD	%R9,%RSI

  (54) 0x6b58 DEC	%RDX

  (54) 0x6b5b VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (54) 0x6b5f VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (54) 0x6b63 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (54) 0x6b68 JNE	6b40

0x6b6a JMP	6b7c

0x6b6c MOV	0x40(%RSP),%R11

0x6b71 MOV	0x88(%RSP),%R14

0x6b79 MOV	%RCX,%R8

0x6b7c MOV	0x248(%RSP),%R15

0x6b84 SUB	%R11,%RCX

0x6b87 CMP	$-0x8,%RCX

0x6b8b JA	6aae

0x6b91 MOV	0x38(%RSP),%RDI

0x6b96 LEA	0x7(%R8),%RCX

0x6b9a LEA	0x4(%R8),%RBX

0x6b9e LEA	0x3(%R8),%R13

0x6ba2 LEA	0x1(%R8),%RDX

0x6ba6 IMUL	%RDI,%RCX

0x6baa MOV	%RDI,%RSI

0x6bad IMUL	%RDI,%RBX

0x6bb1 IMUL	%RDI,%R13

0x6bb5 IMUL	%RDI,%RDX

0x6bb9 IMUL	%R8,%RSI

0x6bbd MOV	%RCX,0x140(%RSP)

0x6bc5 LEA	0x6(%R8),%RCX

0x6bc9 IMUL	%RDI,%RCX

0x6bcd MOV	%RCX,0x120(%RSP)

0x6bd5 LEA	0x5(%R8),%RCX

0x6bd9 IMUL	%RDI,%RCX

0x6bdd MOV	%RCX,0xa0(%RSP)

0x6be5 LEA	0x2(%R8),%RCX

0x6be9 IMUL	%RDI,%RCX

0x6bed MOV	0x30(%RSP),%RDI

0x6bf2 NOPW	%CS:(%RAX,%RAX,1)

  (53) 0x6c00 LEA	(%RAX,%R8,1),%R9D

  (53) 0x6c04 LEA	0x6(%RAX,%R8,1),%R10D

  (53) 0x6c09 VMOVSS	(%R12,%R9,4),%XMM1

  (53) 0x6c0f LEA	(%RSI,%RDI,1),%R9D

  (53) 0x6c13 VMOVSS	(%R14,%R9,4),%XMM2

  (53) 0x6c19 LEA	0x1(%RAX,%R8,1),%R9D

  (53) 0x6c1e VMOVSS	(%R12,%R10,4),%XMM13

  (53) 0x6c24 VMOVSS	(%R12,%R9,4),%XMM3

  (53) 0x6c2a LEA	(%RDX,%RDI,1),%R9D

  (53) 0x6c2e VMOVSS	(%R14,%R9,4),%XMM4

  (53) 0x6c34 LEA	0x2(%RAX,%R8,1),%R9D

  (53) 0x6c39 VMOVSS	(%R12,%R9,4),%XMM5

  (53) 0x6c3f LEA	(%RCX,%RDI,1),%R9D

  (53) 0x6c43 VMOVSS	(%R14,%R9,4),%XMM6

  (53) 0x6c49 LEA	0x3(%RAX,%R8,1),%R9D

  (53) 0x6c4e VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x6c52 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (53) 0x6c56 VMOVSS	(%R12,%R9,4),%XMM7

  (53) 0x6c5c LEA	(%R13,%RDI,1),%R9D

  (53) 0x6c61 VMOVSS	(%R14,%R9,4),%XMM8

  (53) 0x6c67 LEA	0x4(%RAX,%R8,1),%R9D

  (53) 0x6c6c VFMADD213SD	%XMM0,%XMM1,%XMM2

  (53) 0x6c71 VCVTSS2SD	%XMM3,%XMM3,%XMM0

  (53) 0x6c75 VMOVSS	(%R12,%R9,4),%XMM9

  (53) 0x6c7b LEA	(%RBX,%RDI,1),%R9D

  (53) 0x6c7f VMOVSS	(%R14,%R9,4),%XMM10

  (53) 0x6c85 LEA	0x5(%RAX,%R8,1),%R9D

  (53) 0x6c8a VCVTSS2SD	%XMM4,%XMM4,%XMM1

  (53) 0x6c8e VMOVSS	(%R12,%R9,4),%XMM11

  (53) 0x6c94 MOV	0xa0(%RSP),%R9

  (53) 0x6c9c VFMADD213SD	%XMM2,%XMM0,%XMM1

  (53) 0x6ca1 VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (53) 0x6ca5 LEA	(%R9,%RDI,1),%R9D

  (53) 0x6ca9 VCVTSS2SD	%XMM6,%XMM6,%XMM2

  (53) 0x6cad VMOVSS	(%R14,%R9,4),%XMM12

  (53) 0x6cb3 MOV	0x120(%RSP),%R9

  (53) 0x6cbb VFMADD213SD	%XMM1,%XMM0,%XMM2

  (53) 0x6cc0 VCVTSS2SD	%XMM7,%XMM7,%XMM0

  (53) 0x6cc4 ADD	%EDI,%R9D

  (53) 0x6cc7 VCVTSS2SD	%XMM8,%XMM8,%XMM1

  (53) 0x6ccc VMOVSS	(%R14,%R9,4),%XMM14

  (53) 0x6cd2 LEA	0x7(%RAX,%R8,1),%R9D

  (53) 0x6cd7 ADD	$0x8,%R8

  (53) 0x6cdb VMOVSS	(%R12,%R9,4),%XMM15

  (53) 0x6ce1 MOV	0x140(%RSP),%R9

  (53) 0x6ce9 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (53) 0x6cee VCVTSS2SD	%XMM9,%XMM9,%XMM0

  (53) 0x6cf3 VCVTSS2SD	%XMM10,%XMM10,%XMM2

  (53) 0x6cf8 ADD	%EDI,%R9D

  (53) 0x6cfb ADD	%R15,%RDI

  (53) 0x6cfe VMOVSS	(%R14,%R9,4),%XMM16

  (53) 0x6d05 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (53) 0x6d0a VCVTSS2SD	%XMM11,%XMM11,%XMM0

  (53) 0x6d0f VCVTSS2SD	%XMM12,%XMM12,%XMM1

  (53) 0x6d14 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (53) 0x6d19 VCVTSS2SD	%XMM13,%XMM13,%XMM0

  (53) 0x6d1e VCVTSS2SD	%XMM14,%XMM14,%XMM2

  (53) 0x6d23 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (53) 0x6d28 VCVTSS2SD	%XMM15,%XMM15,%XMM1

  (53) 0x6d2d VCVTSS2SD	%XMM16,%XMM16,%XMM0

  (53) 0x6d33 VFMADD213SD	%XMM2,%XMM1,%XMM0

  (53) 0x6d38 CMP	%R8,%R11

  (53) 0x6d3b JNE	6c00

0x6d41 JMP	6aae

0x6d46 CMP	$0x10,%R13D

0x6d4a JAE	6d5b

0x6d4c MOV	0x88(%RSP),%RDI

0x6d54 XOR	%EDX,%EDX

0x6d56 JMP	6e14

0x6d5b MOV	0x3a0(%RSP),%RSI

0x6d63 MOV	0x88(%RSP),%RDI

0x6d6b VXORPS	%XMM0,%XMM0,%XMM0

0x6d6f XOR	%ECX,%ECX

0x6d71 VXORPS	%XMM1,%XMM1,%XMM1

0x6d75 VXORPS	%XMM2,%XMM2,%XMM2

0x6d79 VXORPS	%XMM3,%XMM3,%XMM3

  (55) 0x6d7d LEA	(%RAX,%RCX,1),%EDX

  (55) 0x6d80 VCVTPS2PD	(%R12,%RDX,4),%YMM4

  (55) 0x6d86 VCVTPS2PD	0x10(%R12,%RDX,4),%YMM5

  (55) 0x6d8d VCVTPS2PD	0x20(%R12,%RDX,4),%YMM6

  (55) 0x6d94 VCVTPS2PD	0x30(%R12,%RDX,4),%YMM7

  (55) 0x6d9b LEA	(%R15,%RCX,1),%EDX

  (55) 0x6d9f ADD	$0x10,%RCX

  (55) 0x6da3 VCVTPS2PD	(%RDI,%RDX,4),%YMM8

  (55) 0x6da8 VCVTPS2PD	0x10(%RDI,%RDX,4),%YMM9

  (55) 0x6dae VFMADD231PD	%YMM8,%YMM4,%YMM0

  (55) 0x6db3 VFMADD231PD	%YMM9,%YMM5,%YMM1

  (55) 0x6db8 VCVTPS2PD	0x20(%RDI,%RDX,4),%YMM8

  (55) 0x6dbe VCVTPS2PD	0x30(%RDI,%RDX,4),%YMM5

  (55) 0x6dc4 VFMADD231PD	%YMM8,%YMM6,%YMM2

  (55) 0x6dc9 VFMADD231PD	%YMM5,%YMM7,%YMM3

  (55) 0x6dce CMP	%RCX,%RSI

  (55) 0x6dd1 JNE	6d7d

0x6dd3 VADDPD	%YMM0,%YMM1,%YMM0

0x6dd7 VADDPD	%YMM2,%YMM3,%YMM1

0x6ddb VADDPD	%YMM0,%YMM1,%YMM0

0x6ddf VEXTRACTF128	$0x1,%YMM0,%XMM1

0x6de5 VADDPD	%XMM1,%XMM0,%XMM0

0x6de9 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x6dee VADDSD	%XMM1,%XMM0,%XMM0

0x6df2 CMP	%ESI,%R13D

0x6df5 JE	6aa9

0x6dfb TESTB	$0xc,0x58(%RSP)

0x6e00 MOV	0x88(%RSP),%RDI

0x6e08 MOV	%RSI,%RDX

0x6e0b MOV	%RSI,%RCX

0x6e0e JE	6b10

0x6e14 MOV	0x3b0(%RSP),%RSI

0x6e1c MOV	0x30(%RSP),%R8

0x6e21 VMOVQ	%XMM0,%XMM0

  (56) 0x6e25 LEA	(%RAX,%RDX,1),%ECX

  (56) 0x6e28 VCVTPS2PD	(%R12,%RCX,4),%YMM1

  (56) 0x6e2e LEA	(%R8,%RDX,1),%ECX

  (56) 0x6e32 ADD	$0x4,%RDX

  (56) 0x6e36 VCVTPS2PD	(%RDI,%RCX,4),%YMM2

  (56) 0x6e3b VFMADD231PD	%YMM2,%YMM1,%YMM0

  (56) 0x6e40 CMP	%RDX,%RSI

  (56) 0x6e43 JNE	6e25

0x6e45 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x6e4b MOV	0x40(%RSP),%R11

0x6e50 MOV	%RSI,%RCX

0x6e53 VADDPD	%XMM1,%XMM0,%XMM0

0x6e57 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x6e5c VADDSD	%XMM1,%XMM0,%XMM0

0x6e60 CMP	%ESI,%R11D

0x6e63 JE	6aae

0x6e69 JMP	6b10

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.22
CQA speedup if FP arith vectorized	2.60
CQA speedup if fully vectorized	10.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.88
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.95
CQA cycles if fully vectorized	1.19
Front-end cycles	12.88
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	103.00
Nb uops	103.00
Nb loads	26.00
Nb stores	5.00
Nb stack references	16.00
FLOP/cycle	1.40
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.55
Bytes prefetched	0.00
Bytes loaded	190.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	62.50
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	17.48
Vector-efficiency ratio load	11.59
Vector-efficiency ratio store	11.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	29.69
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.10

Metric	Value
CQA speedup if no scalar integer	3.22
CQA speedup if FP arith vectorized	2.60
CQA speedup if fully vectorized	10.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.88
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.95
CQA cycles if fully vectorized	1.19
Front-end cycles	12.88
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	103.00
Nb uops	103.00
Nb loads	26.00
Nb stores	5.00
Nb stack references	16.00
FLOP/cycle	1.40
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.55
Bytes prefetched	0.00
Bytes loaded	190.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	62.50
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	17.48
Vector-efficiency ratio load	11.59
Vector-efficiency ratio store	11.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	29.69
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.88 to 4.00 cycles (3.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
62% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: addition or subtraction

The binary loop is loading 190 bytes (23 double precision FP elements). The binary loop is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	103
loop length	484
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.88 cycles
front end	12.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	7.75	7.75	7.75	7.75	2.50	2.50	4.00	4.00	0.50	0.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	7.75	7.75	7.75	7.75	2.50	2.50	4.00	4.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.88
Dispatch	7.75
Overall L1	12.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	32%
load	0%
store	0%
mul	0%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	17%
load	11%
store	11%
mul	12%
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.88 cycles. At this rate:

5% of peak load performance is reached (14.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.88 to 7.75 cycles (1.66x speedup).

ASM code

In the binary file, the address of the loop is: 6ae5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x170(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1b0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV %R11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM0,(%RDX,%RCX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP 0x28(%RSP),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 6a5d <main+0x3c8d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 6b0e <main+0x3d3e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0x2f8(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0xe0(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 6d46 <main+0x3f76>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6b6c <main+0x3d9c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x38(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x30(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 6b7c <main+0x3dac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x248(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x7(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%R8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%R8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %RDI,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R8,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x6(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x5(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 6d5b <main+0x3f8b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6e14 <main+0x4044>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x3a0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %ESI,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 6aa9 <main+0x3cd9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TESTB $0xc,0x58(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (1.6%)
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JE 6b10 <main+0x3d40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x3b0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
JMP 6b10 <main+0x3d40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.88 to 4.00 cycles (3.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
62% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 18 FP arithmetical operations:

18: addition or subtraction

The binary loop is loading 190 bytes (23 double precision FP elements). The binary loop is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	103
loop length	484
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.88 cycles
front end	12.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	7.75	7.75	7.75	7.75	2.50	2.50	4.00	4.00	0.50	0.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	7.75	7.75	7.75	7.75	2.50	2.50	4.00	4.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.88
Dispatch	7.75
Overall L1	12.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	32%
load	0%
store	0%
mul	0%
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	17%
load	11%
store	11%
mul	12%
add-sub	29%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.88 cycles. At this rate:

5% of peak load performance is reached (14.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6ae5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x170(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1b0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV %R11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM0,(%RDX,%RCX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP 0x28(%RSP),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 6a5d <main+0x3c8d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 6b0e <main+0x3d3e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0x2f8(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0xe0(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 6d46 <main+0x3f76>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6b6c <main+0x3d9c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x38(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD 0x30(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 6b7c <main+0x3dac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x248(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x7(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%R8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%R8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %RDI,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R8,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x6(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x5(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 6d5b <main+0x3f8b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6e14 <main+0x4044>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x3a0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %ESI,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 6aa9 <main+0x3cd9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TESTB $0xc,0x58(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (1.6%)
MOV 0x88(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JE 6b10 <main+0x3d40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x3b0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV 0x40(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6aae <main+0x3cde>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
JMP 6b10 <main+0x3d40>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code