OV - attention-clang-znver5-256 - Loop 41 - attention-clang-znver5-256

	Loop Id: 41	Module: attention-clang-znver5-256	Source: attention_v2.cpp:30-31	Coverage: 6.53%

0x4f10 LEA	(%RCX,%R9,1),%R11D

0x4f14 VMOVSS	(%R8,%R11,4),%XMM1    [3]

0x4f1a MOV	%R10D,%R11D

0x4f1d VMOVSS	(%R14,%R11,4),%XMM2    [2]

0x4f23 LEA	0x1(%RCX,%R9,1),%R11D

0x4f28 VMOVSS	(%R8,%R11,4),%XMM3    [3]

0x4f2e LEA	(%RBX,%R10,1),%R11D

0x4f32 LEA	0x6(%RCX,%R9,1),%EBX

0x4f37 VMOVSS	(%R14,%R11,4),%XMM4    [2]

0x4f3d LEA	0x2(%RCX,%R9,1),%R11D

0x4f42 VMOVSS	(%R8,%RBX,4),%XMM13    [3]

0x4f48 MOV	0x38(%RSP),%RBX    [1]

0x4f4d VMOVSS	(%R8,%R11,4),%XMM5    [3]

0x4f53 LEA	(%RSI,%R10,1),%R11D

0x4f57 VMOVSS	(%R14,%R11,4),%XMM6    [2]

0x4f5d LEA	0x3(%RCX,%R9,1),%R11D

0x4f62 VCVTSS2SD	%XMM1,%XMM1,%XMM1

0x4f66 VCVTSS2SD	%XMM2,%XMM2,%XMM2

0x4f6a VMOVSS	(%R8,%R11,4),%XMM7    [3]

0x4f70 LEA	(%RDX,%R10,1),%R11D

0x4f74 VMOVSS	(%R14,%R11,4),%XMM8    [2]

0x4f7a LEA	0x4(%RCX,%R9,1),%R11D

0x4f7f VFMADD213SD	%XMM0,%XMM1,%XMM2

0x4f84 VCVTSS2SD	%XMM3,%XMM3,%XMM0

0x4f88 VMOVSS	(%R8,%R11,4),%XMM9    [3]

0x4f8e LEA	(%R15,%R10,1),%R11D

0x4f92 VMOVSS	(%R14,%R11,4),%XMM10    [2]

0x4f98 LEA	0x5(%RCX,%R9,1),%R11D

0x4f9d VCVTSS2SD	%XMM4,%XMM4,%XMM1

0x4fa1 VMOVSS	(%R8,%R11,4),%XMM11    [3]

0x4fa7 LEA	(%R13,%R10,1),%R11D

0x4fac VMOVSS	(%R14,%R11,4),%XMM12    [2]

0x4fb2 LEA	(%R12,%R10,1),%R11D

0x4fb6 VMOVSS	(%R14,%R11,4),%XMM14    [2]

0x4fbc LEA	0x7(%RCX,%R9,1),%R11D

0x4fc1 ADD	$0x8,%R9

0x4fc5 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x4fca VCVTSS2SD	%XMM5,%XMM5,%XMM0

0x4fce VMOVSS	(%R8,%R11,4),%XMM15    [3]

0x4fd4 LEA	(%RDI,%R10,1),%R11D

0x4fd8 ADD	%RAX,%R10

0x4fdb VMOVSS	(%R14,%R11,4),%XMM16    [2]

0x4fe2 VCVTSS2SD	%XMM6,%XMM6,%XMM2

0x4fe6 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x4feb VCVTSS2SD	%XMM7,%XMM7,%XMM0

0x4fef VCVTSS2SD	%XMM8,%XMM8,%XMM1

0x4ff4 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x4ff9 VCVTSS2SD	%XMM9,%XMM9,%XMM0

0x4ffe VCVTSS2SD	%XMM10,%XMM10,%XMM2

0x5003 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x5008 VCVTSS2SD	%XMM11,%XMM11,%XMM0

0x500d VCVTSS2SD	%XMM12,%XMM12,%XMM1

0x5012 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x5017 VCVTSS2SD	%XMM13,%XMM13,%XMM0

0x501c VCVTSS2SD	%XMM14,%XMM14,%XMM2

0x5021 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x5026 VCVTSS2SD	%XMM15,%XMM15,%XMM1

0x502b VCVTSS2SD	%XMM16,%XMM16,%XMM0

0x5031 VFMADD213SD	%XMM2,%XMM1,%XMM0

0x5036 CMP	%R9,0x1c0(%RSP)    [1]

0x503e JNE	4f10

/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.71
CQA speedup if fully vectorized	14.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.82
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.69
CQA cycles if fully vectorized	2.26
Front-end cycles	8.38
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	67.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.50
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.71
CQA speedup if fully vectorized	14.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.82
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.69
CQA cycles if fully vectorized	2.26
Front-end cycles	8.38
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	67.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.50
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 2.26 cycles (14.14x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	61
nb uops	67
loop length	308
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00
cycles	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.38
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (2.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4f10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R9,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R8,%R11,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS (%R14,%R11,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R8,%R11,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RCX,%R9,1),%EBX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%R11,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R8,%RBX,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x38(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSS (%R8,%R11,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R15,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R13,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R9,0x1c0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 4f10 <main+0x2140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	61
nb uops	67
loop length	308
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00
cycles	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.38
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (2.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4f10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R9,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R8,%R11,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS (%R14,%R11,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R8,%R11,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RCX,%R9,1),%EBX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%R11,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R8,%RBX,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x38(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSS (%R8,%R11,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R15,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R13,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R8,%R11,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R9,0x1c0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 4f10 <main+0x2140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code