OV - attention-clang-znver5-256 - Loop 100 - attention-clang-znver5-256

	Loop Id: 100	Module: attention-clang-znver5-256	Source: random.tcc:404-406	Coverage: 0.06%

0x3ab0 VMOVDQU	0x4a0(%RSP,%RDX,8),%YMM3    [1]

0x3ab9 VMOVDQU	0x4c0(%RSP,%RDX,8),%YMM4    [1]

0x3ac2 VMOVDQU	0x4e0(%RSP,%RDX,8),%YMM5    [1]

0x3acb VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

0x3ad2 VMOVDQU	0x500(%RSP,%RDX,8),%YMM2    [1]

0x3adb VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

0x3ae2 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

0x3ae9 VPAND	%YMM3,%YMM15,%YMM10

0x3aed VPAND	%YMM4,%YMM15,%YMM11

0x3af1 VPAND	%YMM5,%YMM15,%YMM12

0x3af5 VPTESTMQ	%YMM16,%YMM3,%K1

0x3afb VPTESTMQ	%YMM16,%YMM4,%K2

0x3b01 VPTESTMQ	%YMM16,%YMM5,%K3

0x3b07 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

0x3b0e VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

0x3b15 VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

0x3b1c VPSRLQ	$0x1,%YMM10,%YMM6

0x3b22 VPSRLQ	$0x1,%YMM11,%YMM7

0x3b28 VPSRLQ	$0x1,%YMM12,%YMM8

0x3b2e VPXOR	0x1100(%RSP,%RDX,8),%YMM6,%YMM6    [1]

0x3b37 VPXOR	0x1120(%RSP,%RDX,8),%YMM7,%YMM7    [1]

0x3b40 VPXOR	0x1140(%RSP,%RDX,8),%YMM8,%YMM8    [1]

0x3b49 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

0x3b50 VPAND	%YMM2,%YMM15,%YMM13

0x3b54 VPTESTMQ	%YMM16,%YMM2,%K4

0x3b5a VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

0x3b61 VPSRLQ	$0x1,%YMM13,%YMM9

0x3b67 VPXOR	0x1160(%RSP,%RDX,8),%YMM9,%YMM9    [1]

0x3b70 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

0x3b76 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

0x3b7c VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

0x3b82 VMOVDQU	%YMM6,0x498(%RSP,%RDX,8)    [1]

0x3b8b VMOVDQU	%YMM7,0x4b8(%RSP,%RDX,8)    [1]

0x3b94 VMOVDQU	%YMM8,0x4d8(%RSP,%RDX,8)    [1]

0x3b9d VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

0x3ba3 VMOVDQU	%YMM9,0x4f8(%RSP,%RDX,8)    [1]

0x3bac ADD	$0x10,%RDX

0x3bb0 CMP	$0xe0,%RDX

0x3bb7 JNE	3ab0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 404 - 406

--------------------------------------------------------------------------------

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12, P13,
Function	main
Source	random.tcc:404-406
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	3.50
Front-end cycles	4.75
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	38.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.86
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P10, P11, P12, P13,
Function	main
Source	random.tcc:404-406
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	3.50
Front-end cycles	4.75
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	2.00
P15 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	38.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.86
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-406
Module	attention-clang-znver5-256

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:404-406.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	39
nb uops	38
loop length	269
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	7.00	7.00	7.00	7.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	7.00	7.00	7.00	7.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Dispatch	7.00
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

14% of peak load performance is reached (36.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU 0x4a0(%RSP,%RDX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x4c0(%RSP,%RDX,8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x4e0(%RSP,%RDX,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM2,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x500(%RSP,%RDX,8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM3,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM4,%YMM5,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VPAND %YMM3,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPAND %YMM4,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPAND %YMM5,%YMM15,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTESTMQ %YMM16,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTESTMQ %YMM16,%YMM4,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTESTMQ %YMM16,%YMM5,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPSRLQ $0x1,%YMM10,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1100(%RSP,%RDX,8),%YMM6,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1120(%RSP,%RDX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1140(%RSP,%RDX,8),%YMM8,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM5,%YMM2,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VPAND %YMM2,%YMM15,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTESTMQ %YMM16,%YMM2,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPSRLQ $0x1,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1160(%RSP,%RDX,8),%YMM9,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXORQ %YMM17,%YMM6,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPXORQ %YMM17,%YMM7,%YMM7{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPXORQ %YMM17,%YMM8,%YMM8{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VMOVDQU %YMM6,0x498(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU %YMM7,0x4b8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU %YMM8,0x4d8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPXORQ %YMM17,%YMM9,%YMM9{%K4}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VMOVDQU %YMM9,0x4f8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0xe0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 3ab0 <main+0xce0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	random.tcc:404-406
Module	attention-clang-znver5-256

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:404-406.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 256 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	39
nb uops	38
loop length	269
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	16
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	7.00	7.00	7.00	7.00	2.00	2.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	3.00	3.00	3.00	3.00	7.00	7.00	7.00	7.00	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Dispatch	7.00
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

14% of peak load performance is reached (36.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3ab0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU 0x4a0(%RSP,%RDX,8),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x4c0(%RSP,%RDX,8),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x4e0(%RSP,%RDX,8),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM2,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x500(%RSP,%RDX,8),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM3,%YMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM4,%YMM5,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VPAND %YMM3,%YMM15,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPAND %YMM4,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPAND %YMM5,%YMM15,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTESTMQ %YMM16,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTESTMQ %YMM16,%YMM4,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTESTMQ %YMM16,%YMM5,%K3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPSRLQ $0x1,%YMM10,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPSRLQ $0x1,%YMM12,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1100(%RSP,%RDX,8),%YMM6,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1120(%RSP,%RDX,8),%YMM7,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1140(%RSP,%RDX,8),%YMM8,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VALIGNQ $0x3,%YMM5,%YMM2,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (50.0%)
VPAND %YMM2,%YMM15,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPTESTMQ %YMM16,%YMM2,%K4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPSRLQ $0x1,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (50.0%)
VPXOR 0x1160(%RSP,%RDX,8),%YMM9,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (50.0%)
VPXORQ %YMM17,%YMM6,%YMM6{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPXORQ %YMM17,%YMM7,%YMM7{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VPXORQ %YMM17,%YMM8,%YMM8{%K3}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VMOVDQU %YMM6,0x498(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU %YMM7,0x4b8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU %YMM8,0x4d8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPXORQ %YMM17,%YMM9,%YMM9{%K4}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (50.0%)
VMOVDQU %YMM9,0x4f8(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0xe0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 3ab0 <main+0xce0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code