OV - attention-gcc-znver5-512 - Loop 31 - attention-gcc-znver5-512

	Loop Id: 31	Module: attention-gcc-znver5-512	Source: attention_v2.cpp:43-61	Coverage: 0.07%

  (30) 0x402b80 MOV	-0x40(%RBP),%ESI

  (30) 0x402b83 VBROADCASTSS	0x1677(%RIP),%ZMM0

  (30) 0x402b8d MOV	-0x40(%RBP),%EDI

  (30) 0x402b90 MOV	%R14,%RAX

  (30) 0x402b93 SHR	$0x4,%ESI

  (30) 0x402b96 SAL	$0x6,%RSI

  (30) 0x402b9a ADD	%R14,%RSI

  (30) 0x402b9d NOPL	(%RAX)

    (29) 0x402ba0 VMAXPS	(%RAX),%ZMM0,%ZMM0

    (29) 0x402ba6 ADD	$0x40,%RAX

    (29) 0x402baa CMP	%RAX,%RSI

    (29) 0x402bad JNE	402ba0

  (30) 0x402baf VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

  (30) 0x402bb6 VMOVAPS	%YMM0,%YMM1

  (30) 0x402bba VMAXPS	%YMM0,%YMM3,%YMM2

  (30) 0x402bbe VEXTRACTF32X4	$0x1,%YMM2,%XMM0

  (30) 0x402bc5 VMAXPS	%XMM2,%XMM0,%XMM0

  (30) 0x402bc9 VMOVHLPS	%XMM0,%XMM0,%XMM2

  (30) 0x402bcd VMAXPS	%XMM0,%XMM2,%XMM2

  (30) 0x402bd1 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

  (30) 0x402bd6 VMAXPS	%XMM2,%XMM0,%XMM0

  (30) 0x402bda TEST	$0xf,%DIL

  (30) 0x402bde JE	402c9a

0x402be4 MOV	%EDI,%EAX

0x402be6 VMAXPS	%YMM3,%YMM1,%YMM1

0x402bea AND	$-0x10,%EAX

0x402bed MOV	%EAX,%ESI

0x402bef MOV	%R15D,%EDI

0x402bf2 SUB	%EAX,%EDI

0x402bf4 CMP	$0x6,%EDI

0x402bf7 JBE	402c32

0x402bf9 ADD	-0x48(%RBP),%RAX

0x402bfd MOV	-0x88(%RBP),%RCX

0x402c04 INC	%EDI

0x402c06 VMAXPS	(%RCX,%RAX,4),%YMM1,%YMM0

0x402c0b VEXTRACTF32X4	$0x1,%YMM0,%XMM1

0x402c12 VMAXPS	%XMM0,%XMM1,%XMM0

0x402c16 VMOVHLPS	%XMM0,%XMM0,%XMM1

0x402c1a VMAXPS	%XMM0,%XMM1,%XMM1

0x402c1e VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

0x402c23 VMAXPS	%XMM1,%XMM0,%XMM0

0x402c27 TEST	$0x7,%DIL

0x402c2b JE	402c9a

0x402c2d AND	$-0x8,%EDI

0x402c30 ADD	%EDI,%ESI

0x402c32 MOVSXD	%ESI,%RDI

0x402c35 VMAXSS	(%R14,%RDI,4),%XMM0,%XMM0

0x402c3b LEA	(,%RDI,4),%RAX

0x402c43 CMP	%ESI,%R15D

0x402c46 JLE	402c9a

0x402c48 LEA	0x2(%RSI),%EDI

0x402c4b VMAXSS	0x4(%R14,%RAX,1),%XMM0,%XMM0

0x402c52 CMP	%EDI,%R15D

0x402c55 JL	402c9a

0x402c57 LEA	0x3(%RSI),%EDI

0x402c5a VMAXSS	0x8(%R14,%RAX,1),%XMM0,%XMM0

0x402c61 CMP	%EDI,%R15D

0x402c64 JL	402c9a

0x402c66 LEA	0x4(%RSI),%EDI

0x402c69 VMAXSS	0xc(%R14,%RAX,1),%XMM0,%XMM0

0x402c70 CMP	%R15D,%EDI

0x402c73 JG	402c9a

0x402c75 LEA	0x5(%RSI),%EDI

0x402c78 VMAXSS	0x10(%R14,%RAX,1),%XMM0,%XMM0

0x402c7f CMP	%EDI,%R15D

0x402c82 JL	402c9a

0x402c84 ADD	$0x6,%ESI

0x402c87 VMAXSS	0x14(%R14,%RAX,1),%XMM0,%XMM0

0x402c8e CMP	%ESI,%R15D

0x402c91 JL	402c9a

0x402c93 VMAXSS	0x18(%R14,%RAX,1),%XMM0,%XMM0

  (30) 0x402c9a MOVL	$0,-0x34(%RBP)

  (30) 0x402ca1 VMOVSS	%XMM0,-0x38(%RBP)

  (30) 0x402ca6 MOV	%R14,%R12

  (30) 0x402ca9 VZEROUPPER

  (30) 0x402cac NOPL	(%RAX)

    (27) 0x402cb0 VMOVSS	(%R12),%XMM1

    (27) 0x402cb6 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

    (27) 0x402cbb ADD	$0x4,%R12

    (27) 0x402cbf CALL	401110 <expf@plt>

    (27) 0x402cc4 VADDSS	-0x34(%RBP),%XMM0,%XMM5

    (27) 0x402cc9 VMOVSS	%XMM5,-0x34(%RBP)

    (27) 0x402cce CMP	%R12,%RBX

    (27) 0x402cd1 JNE	402cb0

  (30) 0x402cd3 MOV	-0x60(%RBP),%RAX

  (30) 0x402cd7 MOV	-0x48(%RBP),%RCX

  (30) 0x402cdb MOV	%R14,%R13

  (30) 0x402cde LEA	(%RAX,%RCX,4),%R12

  (30) 0x402ce2 NOPW	%CS:(%RAX,%RAX,1)

  (30) 0x402ced NOPL	(%RAX)

    (28) 0x402cf0 VMOVSS	(%R13),%XMM1

    (28) 0x402cf6 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

    (28) 0x402cfb ADD	$0x4,%R13

    (28) 0x402cff ADD	$0x4,%R12

    (28) 0x402d03 CALL	401110 <expf@plt>

    (28) 0x402d08 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

    (28) 0x402d0d VMOVSS	%XMM0,-0x4(%R12)

    (28) 0x402d14 CMP	%R13,%RBX

    (28) 0x402d17 JNE	402cf0

  (30) 0x402d19 MOV	-0x54(%RBP),%EDX

  (30) 0x402d1c LEA	0x1(%R15),%R8D

  (30) 0x402d20 CMP	%R8D,%EDX

  (30) 0x402d23 JE	402da0

  (30) 0x402d25 INCQ	-0x40(%RBP)

  (30) 0x402d29 MOV	-0x50(%RBP),%R13

  (30) 0x402d2d MOV	%EDX,%EAX

  (30) 0x402d2f MOV	-0x80(%RBP),%RDI

  (30) 0x402d33 MOV	-0x40(%RBP),%R15

  (30) 0x402d37 ADD	%RDI,-0x48(%RBP)

  (30) 0x402d3b XOR	%ESI,%ESI

  (30) 0x402d3d MOV	-0x78(%RBP),%R12

  (30) 0x402d41 ADD	-0x70(%RBP),%R14

  (30) 0x402d45 MOV	%R8D,-0x38(%RBP)

  (30) 0x402d49 MOV	%R13,%RDI

  (30) 0x402d4c SUB	%R15D,%EAX

  (30) 0x402d4f ADD	%R12,%R13

  (30) 0x402d52 ADD	%R12,%RBX

  (30) 0x402d55 LEA	0x4(,%RAX,4),%RDX

  (30) 0x402d5d CALL	401040 <memset@plt>

  (30) 0x402d62 VMOVSS	-0x34(%RBP),%XMM2

  (30) 0x402d67 MOV	-0x68(%RBP),%RAX

  (30) 0x402d6b MOV	%R13,-0x50(%RBP)

  (30) 0x402d6f VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

  (30) 0x402d76 MOV	-0x38(%RBP),%R15D

  (30) 0x402d7a CMP	$0xe,%R15D

  (30) 0x402d7e JG	402b80

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-znver5-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.49
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	micro-operation queue, P12, P13,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.09
Front-end cycles	6.00
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.67
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.10
Vectorization ratio load	12.50
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	38.10
Vector-efficiency ratio all	15.18
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.18

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.49
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	micro-operation queue, P12, P13,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.09
Front-end cycles	6.00
P0 cycles	4.83
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.67
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.10
Vectorization ratio load	12.50
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	38.10
Vector-efficiency ratio all	15.18
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.18

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:48

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes (19 single precision FP elements).

General properties

nb instructions	48
nb uops	48
loop length	182
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	2.50	2.50	2.50	2.50	1.50	1.50	6.00	6.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	2.50	2.50	2.50	2.50	1.50	1.50	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	53%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	15%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

4% of peak load performance is reached (12.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.83 cycles (1.24x speedup).

ASM code

In the binary file, the address of the loop is: 402bef

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMAXPS %YMM3,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
AND $-0x10,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SUB %EAX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 402c32 <_Z7softmaxPKfPfS1_i+0x142>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
ADD -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXPS (%RCX,%RAX,4),%YMM1,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1-2	0.25	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
TEST $0x7,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
AND $-0x8,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ESI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS (%R14,%RDI,4),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
LEA (,%RDI,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x2(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x4(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x3(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x8(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x4(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0xc(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x5(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x10(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
ADD $0x6,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x14(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMAXSS 0x18(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:48

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes (19 single precision FP elements).

General properties

nb instructions	48
nb uops	48
loop length	182
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	2.50	2.50	2.50	2.50	1.50	1.50	6.00	6.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	2.50	2.50	2.50	2.50	1.50	1.50	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	53%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	38%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	15%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

4% of peak load performance is reached (12.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 402bef

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMAXPS %YMM3,%YMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
AND $-0x10,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SUB %EAX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 402c32 <_Z7softmaxPKfPfS1_i+0x142>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
ADD -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXPS (%RCX,%RAX,4),%YMM1,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	vect (50.0%)
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1-2	0.25	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
TEST $0x7,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
AND $-0x8,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ESI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS (%R14,%RDI,4),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
LEA (,%RDI,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x2(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x4(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x3(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x8(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x4(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0xc(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x5(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x10(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
ADD $0x6,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXSS 0x14(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 402c9a <_Z7softmaxPKfPfS1_i+0x1aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMAXSS 0x18(%R14,%RAX,1),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	2	0.50	scal (6.3%)

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code