OV - attention-gcc-znver5-512 - Loop 19 - attention-gcc-znver5-512

	Loop Id: 19	Module: attention-gcc-znver5-512	Source: stl_algobase.h:925-1143 [...]	Coverage: 0.07%

0x401493 MOV	-0x27a0(%RBP),%RAX

0x40149a LEA	0x4(%RBX),%RDI

0x40149e XOR	%ESI,%ESI

0x4014a0 MOV	%R8,-0x27b8(%RBP)

0x4014a7 MOV	%R9,-0x2798(%RBP)

0x4014ae LEA	-0x4(%RAX),%RDX

0x4014b2 CALL	401040 <memset@plt>

0x4014b7 MOV	-0x2798(%RBP),%R9

0x4014be MOV	-0x27b8(%RBP),%R8

0x4014c5 MOV	$0x1fffffffffffffff,%RAX

0x4014cf CMP	-0x2810(%RBP),%RAX

0x4014d6 JB	4012c5

0x4014dc MOV	-0x2820(%RBP),%EAX

0x4014e2 DEC	%EAX

0x4014e4 CLTQ

0x4014e6 MOV	%RAX,-0x2840(%RBP)

  (20) 0x4014ed MOV	-0x27a8(%RBP),%RDI

  (20) 0x4014f4 MOV	%R8,-0x27b8(%RBP)

  (20) 0x4014fb MOV	%R9,-0x2798(%RBP)

  (20) 0x401502 CALL	401080 <_Znwm@plt>

  (20) 0x401507 CMPQ	$0x1,-0x2810(%RBP)

  (20) 0x40150f MOV	%RAX,-0x27e8(%RBP)

  (20) 0x401516 MOVL	$0,(%RAX)

  (20) 0x40151c MOV	-0x2798(%RBP),%R9

  (20) 0x401523 JE	4024d1

  (20) 0x401529 MOV	-0x27a8(%RBP),%R15

  (20) 0x401530 LEA	0x4(%RAX),%RDI

  (20) 0x401534 XOR	%ESI,%ESI

  (20) 0x401536 MOV	%R9,-0x2798(%RBP)

  (20) 0x40153d LEA	-0x4(%R15),%RDX

  (20) 0x401541 CALL	401040 <memset@plt>

  (20) 0x401546 MOV	%R15,%RDI

  (20) 0x401549 CALL	401080 <_Znwm@plt>

  (20) 0x40154e MOVL	$0,(%RAX)

  (20) 0x401554 LEA	0x4(%RAX),%RDI

  (20) 0x401558 LEA	-0x4(%R15),%RDX

  (20) 0x40155c XOR	%ESI,%ESI

  (20) 0x40155e MOV	%RAX,-0x27c8(%RBP)

  (20) 0x401565 CALL	401040 <memset@plt>

  (20) 0x40156a MOV	%R15,%RDI

  (20) 0x40156d CALL	401080 <_Znwm@plt>

  (20) 0x401572 MOVL	$0,(%RAX)

  (20) 0x401578 LEA	-0x4(%R15),%RDX

  (20) 0x40157c LEA	0x4(%RAX),%RDI

  (20) 0x401580 XOR	%ESI,%ESI

  (20) 0x401582 MOV	%RAX,%R15

  (20) 0x401585 CALL	401040 <memset@plt>

  (20) 0x40158a MOV	-0x27b8(%RBP),%R8

  (20) 0x401591 MOV	-0x2798(%RBP),%R9

  (20) 0x401598 MOV	-0x27a0(%RBP),%RDI

  (20) 0x40159f MOV	%R8,-0x27b8(%RBP)

  (20) 0x4015a6 MOV	%R9,-0x2798(%RBP)

  (20) 0x4015ad CALL	401080 <_Znwm@plt>

  (20) 0x4015b2 MOV	%RAX,-0x27f0(%RBP)

  (20) 0x4015b9 MOVL	$0,(%RAX)

  (20) 0x4015bf MOV	-0x2800(%RBP),%RAX

  (20) 0x4015c6 MOV	-0x2798(%RBP),%R9

  (20) 0x4015cd DEC	%RAX

  (20) 0x4015d0 JE	40246a

  (20) 0x4015d6 MOV	-0x27a0(%RBP),%R13

  (20) 0x4015dd MOV	-0x27f0(%RBP),%RAX

  (20) 0x4015e4 XOR	%ESI,%ESI

  (20) 0x4015e6 MOV	%R9,-0x2798(%RBP)

  (20) 0x4015ed LEA	0x4(%RAX),%RDI

  (20) 0x4015f1 LEA	-0x4(%R13),%RDX

  (20) 0x4015f5 CALL	401040 <memset@plt>

  (20) 0x4015fa MOV	%R13,%RDI

  (20) 0x4015fd CALL	401080 <_Znwm@plt>

  (20) 0x401602 MOVL	$0,(%RAX)

  (20) 0x401608 LEA	0x4(%RAX),%RDI

  (20) 0x40160c LEA	-0x4(%R13),%RDX

  (20) 0x401610 XOR	%ESI,%ESI

  (20) 0x401612 MOV	%RAX,%R12

  (20) 0x401615 CALL	401040 <memset@plt>

  (20) 0x40161a MOV	%R13,%RDI

  (20) 0x40161d CALL	401080 <_Znwm@plt>

  (20) 0x401622 MOVL	$0,(%RAX)

  (20) 0x401628 LEA	0x4(%RAX),%RDI

  (20) 0x40162c LEA	-0x4(%R13),%RDX

  (20) 0x401630 XOR	%ESI,%ESI

  (20) 0x401632 MOV	%RAX,-0x27d0(%RBP)

  (20) 0x401639 CALL	401040 <memset@plt>

  (20) 0x40163e MOV	-0x27a0(%RBP),%RDI

  (20) 0x401645 CALL	401080 <_Znwm@plt>

  (20) 0x40164a MOVL	$0,(%RAX)

  (20) 0x401650 LEA	0x4(%RAX),%RDI

  (20) 0x401654 LEA	-0x4(%R13),%RDX

  (20) 0x401658 XOR	%ESI,%ESI

  (20) 0x40165a MOV	%RAX,-0x27d8(%RBP)

  (20) 0x401661 CALL	401040 <memset@plt>

  (20) 0x401666 MOV	-0x27a0(%RBP),%RDI

  (20) 0x40166d CALL	401080 <_Znwm@plt>

  (20) 0x401672 MOVL	$0,(%RAX)

  (20) 0x401678 LEA	-0x4(%R13),%RDX

  (20) 0x40167c LEA	0x4(%RAX),%RDI

  (20) 0x401680 XOR	%ESI,%ESI

  (20) 0x401682 MOV	%RAX,%R13

  (20) 0x401685 CALL	401040 <memset@plt>

  (20) 0x40168a MOV	-0x27b8(%RBP),%R8

  (20) 0x401691 MOV	-0x2798(%RBP),%R9

  (20) 0x401698 MOV	$0x1fffffffffffffff,%RAX

  (20) 0x4016a2 CMP	-0x2818(%RBP),%RAX

  (20) 0x4016a9 JB	401230

  (20) 0x4016af MOV	-0x27b0(%RBP),%RDI

  (20) 0x4016b6 MOV	%R8,-0x27c0(%RBP)

  (20) 0x4016bd MOV	%R9,-0x2798(%RBP)

  (20) 0x4016c4 CALL	401080 <_Znwm@plt>

  (20) 0x4016c9 CMPQ	$0x1,-0x2818(%RBP)

  (20) 0x4016d1 MOV	%RAX,-0x27b8(%RBP)

  (20) 0x4016d8 MOVL	$0,(%RAX)

  (20) 0x4016de MOV	-0x2798(%RBP),%R9

  (20) 0x4016e5 MOV	-0x27c0(%RBP),%R8

  (20) 0x4016ec JE	402436

  (20) 0x4016f2 MOV	-0x27b0(%RBP),%R14

  (20) 0x4016f9 LEA	0x4(%RAX),%RDI

  (20) 0x4016fd XOR	%ESI,%ESI

  (20) 0x4016ff MOV	%R8,-0x2848(%RBP)

  (20) 0x401706 MOV	%R9,-0x27c0(%RBP)

  (20) 0x40170d LEA	-0x4(%R14),%RDX

  (20) 0x401711 MOV	%RDX,-0x2798(%RBP)

  (20) 0x401718 CALL	401040 <memset@plt>

  (20) 0x40171d MOV	%R14,%RDI

  (20) 0x401720 CALL	401080 <_Znwm@plt>

  (20) 0x401725 MOVL	$0,(%RAX)

  (20) 0x40172b MOV	-0x2798(%RBP),%RDX

  (20) 0x401732 LEA	0x4(%RAX),%RDI

  (20) 0x401736 XOR	%ESI,%ESI

  (20) 0x401738 MOV	%RAX,%R14

  (20) 0x40173b CALL	401040 <memset@plt>

  (20) 0x401740 MOV	-0x27c0(%RBP),%R9

  (20) 0x401747 MOV	-0x2848(%RBP),%R8

  (20) 0x40174e MOV	-0x27e0(%RBP),%RDI

  (20) 0x401755 MOV	%R8,-0x2848(%RBP)

  (20) 0x40175c MOV	%R9,-0x2798(%RBP)

  (20) 0x401763 CALL	401080 <_Znwm@plt>

  (20) 0x401768 CMPQ	$0x1,-0x2828(%RBP)

  (20) 0x401770 MOV	%RAX,-0x27c0(%RBP)

  (20) 0x401777 MOVL	$0,(%RAX)

  (20) 0x40177d MOV	-0x2798(%RBP),%R9

  (20) 0x401784 MOV	-0x2848(%RBP),%R8

  (20) 0x40178b JE	4017c6

  (20) 0x40178d MOV	-0x27e0(%RBP),%RAX

  (20) 0x401794 XOR	%ESI,%ESI

  (20) 0x401796 MOV	%R8,-0x2848(%RBP)

  (20) 0x40179d MOV	%R9,-0x2798(%RBP)

  (20) 0x4017a4 LEA	-0x4(%RAX),%RDX

  (20) 0x4017a8 MOV	-0x27c0(%RBP),%RAX

  (20) 0x4017af LEA	0x4(%RAX),%RDI

  (20) 0x4017b3 CALL	401040 <memset@plt>

  (20) 0x4017b8 MOV	-0x2798(%RBP),%R9

  (20) 0x4017bf MOV	-0x2848(%RBP),%R8

  (20) 0x4017c6 LEA	-0x13b0(%RBP),%RAX

  (20) 0x4017cd LEA	-0x13c0(%RBP),%RSI

  (20) 0x4017d4 LEA	-0x2750(%RBP),%RDI

  (20) 0x4017db MOVL	$0x61666564,-0x13b0(%RBP)

  (20) 0x4017e5 MOV	%R8,-0x2848(%RBP)

  (20) 0x4017ec MOV	%R9,-0x2798(%RBP)

  (20) 0x4017f3 MOV	%RAX,-0x13c0(%RBP)

  (20) 0x4017fa MOVL	$0x746c7561,-0x13ad(%RBP)

  (20) 0x401804 MOVQ	$0x7,-0x13b8(%RBP)

  (20) 0x40180f MOVB	$0,-0x13a9(%RBP)

  (20) 0x401816 CALL	401120 <_ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@plt>

  (20) 0x40181b MOV	-0x13c0(%RBP),%RDI

  (20) 0x401822 LEA	-0x13b0(%RBP),%RAX

  (20) 0x401829 MOV	-0x2798(%RBP),%R9

  (20) 0x401830 MOV	-0x2848(%RBP),%R8

  (20) 0x401837 CMP	%RAX,%RDI

  (20) 0x40183a JE	40185a

  (20) 0x40183c MOV	-0x13b0(%RBP),%RAX

  (20) 0x401843 LEA	0x1(%RAX),%RSI

  (20) 0x401847 CALL	401090 <_ZdlPvm@plt>

  (20) 0x40184c MOV	-0x2848(%RBP),%R8

  (20) 0x401853 MOV	-0x2798(%RBP),%R9

  (20) 0x40185a LEA	-0x2750(%RBP),%RDI

  (20) 0x401861 MOV	%R8,-0x2848(%RBP)

  (20) 0x401868 MOV	%R9,-0x2798(%RBP)

  (20) 0x40186f CALL	4010d0 <_ZNSt13random_device9_M_getvalEv@plt>

  (20) 0x401874 MOV	%EAX,%EAX

  (20) 0x401876 MOV	-0x2798(%RBP),%R9

  (20) 0x40187d MOV	-0x2848(%RBP),%R8

  (20) 0x401884 MOV	$0x1,%ECX

  (20) 0x401889 MOV	%RAX,-0x13c0(%RBP)

  (20) 0x401890 MOV	%RAX,%RDX

  (20) 0x401893 VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x401897 NOPW	%CS:(%RAX,%RAX,1)

  (20) 0x4018a2 NOPW	%CS:(%RAX,%RAX,1)

  (20) 0x4018ad NOPW	%CS:(%RAX,%RAX,1)

  (20) 0x4018b8 NOPL	(%RAX,%RAX,1)

    (1) 0x4018c0 MOV	%RDX,%RAX

    (1) 0x4018c3 SHR	$0x1e,%RAX

    (1) 0x4018c7 XOR	%RDX,%RAX

    (1) 0x4018ca IMUL	$0x6c078965,%RAX,%RAX

    (1) 0x4018d1 LEA	(%RAX,%RCX,1),%EDX

    (1) 0x4018d4 MOV	%RDX,-0x13c0(%RBP,%RCX,8)

    (1) 0x4018dc INC	%RCX

    (1) 0x4018df CMP	$0x270,%RCX

    (1) 0x4018e6 JNE	4018c0

  (20) 0x4018e8 MOV	-0x27a0(%RBP),%RAX

  (20) 0x4018ef MOV	%R12,-0x2848(%RBP)

  (20) 0x4018f6 VMOVSS	0x290e(%RIP),%XMM2

  (20) 0x4018fe VMOVSS	0x290a(%RIP),%XMM3

  (20) 0x401906 VMOVSS	0x28fa(%RIP),%XMM5

  (20) 0x40190e MOVQ	$0x270,-0x40(%RBP)

  (20) 0x401916 MOV	%RBX,-0x2798(%RBP)

  (20) 0x40191d MOV	%R9,-0x2850(%RBP)

  (20) 0x401924 MOV	%R8,-0x2858(%RBP)

  (20) 0x40192b LEA	(%RAX,%RBX,1),%RSI

  (20) 0x40192f MOV	%RSI,%R12

  (20) 0x401932 JMP	4019a8

    (22) 0x401940 MOV	-0x13c0(%RBP,%RAX,8),%RDI

    (22) 0x401948 LEA	0x1(%RAX),%RCX

    (22) 0x40194c ADD	$0x4,%RBX

    (22) 0x401950 MOV	%RCX,-0x40(%RBP)

    (22) 0x401954 MOV	%RDI,%RAX

    (22) 0x401957 SHR	$0xb,%RAX

    (22) 0x40195b MOV	%EAX,%EAX

    (22) 0x40195d XOR	%RDI,%RAX

    (22) 0x401960 MOV	%RAX,%RDI

    (22) 0x401963 SAL	$0x7,%RDI

    (22) 0x401967 AND	$-0x62d3a980,%EDI

    (22) 0x40196d XOR	%RAX,%RDI

    (22) 0x401970 MOV	%RDI,%RAX

    (22) 0x401973 SAL	$0xf,%RAX

    (22) 0x401977 AND	$-0x103a0000,%EAX

    (22) 0x40197c XOR	%RDI,%RAX

    (22) 0x40197f MOV	%RAX,%RDI

    (22) 0x401982 SHR	$0x12,%RDI

    (22) 0x401986 XOR	%RDI,%RAX

    (22) 0x401989 VCVTUSI2SS	%RAX,%XMM1,%XMM0

    (22) 0x40198f VMULSS	%XMM2,%XMM0,%XMM0

    (22) 0x401993 VCMPSS	$0x2,%XMM0,%XMM3,%XMM4

    (22) 0x401998 VBLENDVPS	%XMM4,%XMM5,%XMM0,%XMM0

    (22) 0x40199e VMOVSS	%XMM0,-0x4(%RBX)

    (22) 0x4019a3 CMP	%R12,%RBX

    (22) 0x4019a6 JE	4019e5

    (22) 0x4019a8 MOV	%RCX,%RAX

    (22) 0x4019ab CMP	$0x26f,%RCX

    (22) 0x4019b2 JBE	401940

    (22) 0x4019b4 LEA	-0x13c0(%RBP),%RDI

    (22) 0x4019bb CALL	4033b0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

    (22) 0x4019c0 VMOVSS	0x2840(%RIP),%XMM5

    (22) 0x4019c8 VMOVSS	0x2840(%RIP),%XMM3

    (22) 0x4019d0 VMOVSS	0x2834(%RIP),%XMM2

    (22) 0x4019d8 MOV	-0x40(%RBP),%RAX

    (22) 0x4019dc VXORPS	%XMM1,%XMM1,%XMM1

    (22) 0x4019e0 JMP	401940

  (20) 0x4019e5 MOV	-0x2850(%RBP),%R9

  (20) 0x4019ec MOV	-0x2858(%RBP),%R8

  (20) 0x4019f3 MOV	-0x27c8(%RBP),%R10

  (20) 0x4019fa MOV	-0x27a8(%RBP),%RAX

  (20) 0x401a01 MOV	%R13,-0x2850(%RBP)

  (20) 0x401a08 MOV	%R14,-0x2858(%RBP)

  (20) 0x401a0f VMOVSS	0x27f1(%RIP),%XMM4

  (20) 0x401a17 MOV	-0x27e8(%RBP),%R12

  (20) 0x401a1e MOV	%R15,%R14

  (20) 0x401a21 MOV	%R9,-0x2860(%RBP)

  (20) 0x401a28 MOV	%R8,-0x2868(%RBP)

  (20) 0x401a2f LEA	(%R15,%RAX,1),%RBX

  (20) 0x401a33 MOV	%R10,%R13

  (20) 0x401a36 JMP	401b8f

    (21) 0x401a40 LEA	0x1(%RCX),%RDI

    (21) 0x401a44 MOV	-0x13c0(%RBP,%RCX,8),%RCX

    (21) 0x401a4c MOV	%RDI,-0x40(%RBP)

    (21) 0x401a50 MOV	%RCX,%RAX

    (21) 0x401a53 SHR	$0xb,%RAX

    (21) 0x401a57 MOV	%EAX,%EAX

    (21) 0x401a59 XOR	%RCX,%RAX

    (21) 0x401a5c MOV	%RAX,%RCX

    (21) 0x401a5f SAL	$0x7,%RCX

    (21) 0x401a63 AND	$-0x62d3a980,%ECX

    (21) 0x401a69 XOR	%RAX,%RCX

    (21) 0x401a6c MOV	%RCX,%RAX

    (21) 0x401a6f SAL	$0xf,%RAX

    (21) 0x401a73 AND	$-0x103a0000,%EAX

    (21) 0x401a78 XOR	%RCX,%RAX

    (21) 0x401a7b MOV	%RAX,%RCX

    (21) 0x401a7e SHR	$0x12,%RCX

    (21) 0x401a82 XOR	%RCX,%RAX

    (21) 0x401a85 VCVTUSI2SS	%RAX,%XMM1,%XMM0

    (21) 0x401a8b VMULSS	%XMM2,%XMM0,%XMM0

    (21) 0x401a8f VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

    (21) 0x401a94 VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

    (21) 0x401a9a VMOVSS	%XMM0,(%R12)

    (21) 0x401aa0 CMP	$0x26f,%RDI

    (21) 0x401aa7 JA	401bfe

    (21) 0x401aad MOV	-0x13c0(%RBP,%RDI,8),%RCX

    (21) 0x401ab5 LEA	0x1(%RDI),%R8

    (21) 0x401ab9 MOV	%R8,-0x40(%RBP)

    (21) 0x401abd MOV	%RCX,%RAX

    (21) 0x401ac0 SHR	$0xb,%RAX

    (21) 0x401ac4 MOV	%EAX,%EAX

    (21) 0x401ac6 XOR	%RCX,%RAX

    (21) 0x401ac9 MOV	%RAX,%RCX

    (21) 0x401acc SAL	$0x7,%RCX

    (21) 0x401ad0 AND	$-0x62d3a980,%ECX

    (21) 0x401ad6 XOR	%RAX,%RCX

    (21) 0x401ad9 MOV	%RCX,%RAX

    (21) 0x401adc SAL	$0xf,%RAX

    (21) 0x401ae0 AND	$-0x103a0000,%EAX

    (21) 0x401ae5 XOR	%RCX,%RAX

    (21) 0x401ae8 MOV	%RAX,%RCX

    (21) 0x401aeb SHR	$0x12,%RCX

    (21) 0x401aef XOR	%RCX,%RAX

    (21) 0x401af2 VCVTUSI2SS	%RAX,%XMM1,%XMM0

    (21) 0x401af8 VMULSS	%XMM2,%XMM0,%XMM0

    (21) 0x401afc VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

    (21) 0x401b01 VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

    (21) 0x401b07 VMOVSS	%XMM0,(%R13)

    (21) 0x401b0d CMP	$0x26f,%R8

    (21) 0x401b14 JA	401bcd

    (21) 0x401b1a MOV	-0x13c0(%RBP,%R8,8),%RDI

    (21) 0x401b22 LEA	0x1(%R8),%RCX

    (21) 0x401b26 ADD	$0x4,%R14

    (21) 0x401b2a ADD	$0x4,%R13

    (21) 0x401b2e MOV	%RCX,-0x40(%RBP)

    (21) 0x401b32 ADD	$0x4,%R12

    (21) 0x401b36 MOV	%RDI,%RAX

    (21) 0x401b39 SHR	$0xb,%RAX

    (21) 0x401b3d MOV	%EAX,%EAX

    (21) 0x401b3f XOR	%RDI,%RAX

    (21) 0x401b42 MOV	%RAX,%RDI

    (21) 0x401b45 SAL	$0x7,%RDI

    (21) 0x401b49 AND	$-0x62d3a980,%EDI

    (21) 0x401b4f XOR	%RAX,%RDI

    (21) 0x401b52 MOV	%RDI,%RAX

    (21) 0x401b55 SAL	$0xf,%RAX

    (21) 0x401b59 AND	$-0x103a0000,%EAX

    (21) 0x401b5e XOR	%RDI,%RAX

    (21) 0x401b61 MOV	%RAX,%RDI

    (21) 0x401b64 SHR	$0x12,%RDI

    (21) 0x401b68 XOR	%RDI,%RAX

    (21) 0x401b6b VCVTUSI2SS	%RAX,%XMM1,%XMM0

    (21) 0x401b71 VMULSS	%XMM2,%XMM0,%XMM0

    (21) 0x401b75 VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

    (21) 0x401b7a VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

    (21) 0x401b80 VMOVSS	%XMM0,-0x4(%R14)

    (21) 0x401b86 CMP	%R14,%RBX

    (21) 0x401b89 JE	401c2f

    (21) 0x401b8f CMP	$0x26f,%RCX

    (21) 0x401b96 JBE	401a40

    (21) 0x401b9c LEA	-0x13c0(%RBP),%RDI

    (21) 0x401ba3 CALL	4033b0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

    (21) 0x401ba8 VMOVSS	0x2658(%RIP),%XMM4

    (21) 0x401bb0 VMOVSS	0x2658(%RIP),%XMM3

    (21) 0x401bb8 VMOVSS	0x264c(%RIP),%XMM2

    (21) 0x401bc0 MOV	-0x40(%RBP),%RCX

    (21) 0x401bc4 VXORPS	%XMM1,%XMM1,%XMM1

    (21) 0x401bc8 JMP	401a40

    (21) 0x401bcd LEA	-0x13c0(%RBP),%RDI

    (21) 0x401bd4 CALL	4033b0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

    (21) 0x401bd9 VMOVSS	0x2627(%RIP),%XMM4

    (21) 0x401be1 VMOVSS	0x2627(%RIP),%XMM3

    (21) 0x401be9 VMOVSS	0x261b(%RIP),%XMM2

    (21) 0x401bf1 MOV	-0x40(%RBP),%R8

    (21) 0x401bf5 VXORPS	%XMM1,%XMM1,%XMM1

    (21) 0x401bf9 JMP	401b1a

    (21) 0x401bfe LEA	-0x13c0(%RBP),%RDI

    (21) 0x401c05 CALL	4033b0 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

    (21) 0x401c0a VMOVSS	0x25f6(%RIP),%XMM4

    (21) 0x401c12 VMOVSS	0x25f6(%RIP),%XMM3

    (21) 0x401c1a VMOVSS	0x25ea(%RIP),%XMM2

    (21) 0x401c22 MOV	-0x40(%RBP),%RDI

    (21) 0x401c26 VXORPS	%XMM1,%XMM1,%XMM1

    (21) 0x401c2a JMP	401aad

  (20) 0x401c2f MOV	-0x2860(%RBP),%R9

  (20) 0x401c36 MOV	-0x2868(%RBP),%R8

  (20) 0x401c3d MOV	-0x2848(%RBP),%R12

  (20) 0x401c44 MOV	-0x2850(%RBP),%R13

  (20) 0x401c4b MOV	-0x2798(%RBP),%RBX

  (20) 0x401c52 MOV	-0x2858(%RBP),%R14

  (20) 0x401c59 MOV	%R9,-0x2850(%RBP)

  (20) 0x401c60 MOV	%R8,-0x2848(%RBP)

  (20) 0x401c67 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401c6c MOV	-0x2850(%RBP),%R9

  (20) 0x401c73 MOV	%RAX,-0x2798(%RBP)

  (20) 0x401c7a MOV	-0x2848(%RBP),%R8

  (20) 0x401c81 MOV	-0x27e8(%RBP),%R10

  (20) 0x401c88 XOR	%ESI,%ESI

  (20) 0x401c8a XOR	%EDX,%EDX

  (20) 0x401c8c VXORPS	%XMM1,%XMM1,%XMM1

    (4) 0x401c90 XOR	%R11D,%R11D

    (4) 0x401c93 NOPW	%CS:(%RAX,%RAX,1)

    (4) 0x401c9e XCHG	%AX,%AX

      (3) 0x401ca0 MOV	%R11D,%ECX

      (3) 0x401ca3 VXORPD	%XMM4,%XMM4,%XMM4

      (3) 0x401ca7 XOR	%EAX,%EAX

      (3) 0x401ca9 NOPW	%CS:(%RAX,%RAX,1)

      (3) 0x401cb4 NOPW	%CS:(%RAX,%RAX,1)

      (3) 0x401cbf NOP

        (2) 0x401cc0 LEA	(%RAX,%RSI,1),%EDI

        (2) 0x401cc3 INC	%EAX

        (2) 0x401cc5 VCVTSS2SD	(%RBX,%RDI,4),%XMM1,%XMM0

        (2) 0x401cca MOV	%ECX,%EDI

        (2) 0x401ccc ADD	%R8D,%ECX

        (2) 0x401ccf VCVTSS2SD	(%R10,%RDI,4),%XMM1,%XMM2

        (2) 0x401cd5 VMULSD	%XMM2,%XMM0,%XMM0

        (2) 0x401cd9 VADDSD	%XMM0,%XMM4,%XMM4

        (2) 0x401cdd CMP	%R8D,%EAX

        (2) 0x401ce0 JB	401cc0

      (3) 0x401ce2 VCVTSD2SS	%XMM4,%XMM4,%XMM4

      (3) 0x401ce6 LEA	(%R11,%RSI,1),%EAX

      (3) 0x401cea INC	%R11D

      (3) 0x401ced VMOVSS	%XMM4,(%R12,%RAX,4)

      (3) 0x401cf3 CMP	%R8D,%R11D

      (3) 0x401cf6 JB	401ca0

    (4) 0x401cf8 INC	%EDX

    (4) 0x401cfa ADD	%R8D,%ESI

    (4) 0x401cfd CMP	%EDX,%R9D

    (4) 0x401d00 JNE	401c90

  (20) 0x401d02 MOV	%R9,-0x2858(%RBP)

  (20) 0x401d09 MOV	%R8,-0x2850(%RBP)

  (20) 0x401d10 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401d15 SUB	-0x2798(%RBP),%RAX

  (20) 0x401d1c MOV	%RAX,%RCX

  (20) 0x401d1f MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x401d29 IMUL	%RCX

  (20) 0x401d2c SAR	$0x3f,%RCX

  (20) 0x401d30 MOV	%RDX,%RAX

  (20) 0x401d33 SAR	$0x7,%RAX

  (20) 0x401d37 SUB	%RCX,%RAX

  (20) 0x401d3a ADD	%RAX,-0x2790(%RBP)

  (20) 0x401d41 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401d46 MOV	-0x27c8(%RBP),%RDI

  (20) 0x401d4d MOV	%RAX,-0x2848(%RBP)

  (20) 0x401d54 MOV	-0x27d0(%RBP),%R11

  (20) 0x401d5b MOV	-0x2858(%RBP),%R9

  (20) 0x401d62 XOR	%ESI,%ESI

  (20) 0x401d64 MOV	-0x2850(%RBP),%R8

  (20) 0x401d6b XOR	%EDX,%EDX

  (20) 0x401d6d VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x401d71 NOPW	%CS:(%RAX,%RAX,1)

  (20) 0x401d7c NOPL	(%RAX)

    (7) 0x401d80 MOV	%EDX,-0x2798(%RBP)

    (7) 0x401d86 XOR	%R10D,%R10D

    (7) 0x401d89 NOPL	(%RAX)

      (6) 0x401d90 MOV	%R10D,%ECX

      (6) 0x401d93 VXORPD	%XMM4,%XMM4,%XMM4

      (6) 0x401d97 XOR	%EAX,%EAX

      (6) 0x401d99 NOPW	%CS:(%RAX,%RAX,1)

      (6) 0x401da4 NOPW	%CS:(%RAX,%RAX,1)

      (6) 0x401daf NOPW	%CS:(%RAX,%RAX,1)

      (6) 0x401dba NOPW	(%RAX,%RAX,1)

        (5) 0x401dc0 LEA	(%RAX,%RSI,1),%EDX

        (5) 0x401dc3 INC	%EAX

        (5) 0x401dc5 VCVTSS2SD	(%RBX,%RDX,4),%XMM1,%XMM0

        (5) 0x401dca MOV	%ECX,%EDX

        (5) 0x401dcc ADD	%R8D,%ECX

        (5) 0x401dcf VCVTSS2SD	(%RDI,%RDX,4),%XMM1,%XMM2

        (5) 0x401dd4 VMULSD	%XMM2,%XMM0,%XMM0

        (5) 0x401dd8 VADDSD	%XMM0,%XMM4,%XMM4

        (5) 0x401ddc CMP	%R8D,%EAX

        (5) 0x401ddf JB	401dc0

      (6) 0x401de1 VCVTSD2SS	%XMM4,%XMM4,%XMM4

      (6) 0x401de5 LEA	(%R10,%RSI,1),%EAX

      (6) 0x401de9 INC	%R10D

      (6) 0x401dec VMOVSS	%XMM4,(%R11,%RAX,4)

      (6) 0x401df2 CMP	%R8D,%R10D

      (6) 0x401df5 JB	401d90

    (7) 0x401df7 MOV	-0x2798(%RBP),%EDX

    (7) 0x401dfd ADD	%R8D,%ESI

    (7) 0x401e00 INC	%EDX

    (7) 0x401e02 CMP	%R9D,%EDX

    (7) 0x401e05 JB	401d80

  (20) 0x401e0b MOV	%R9,-0x2858(%RBP)

  (20) 0x401e12 MOV	%R8,-0x2850(%RBP)

  (20) 0x401e19 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401e1e SUB	-0x2848(%RBP),%RAX

  (20) 0x401e25 MOV	%RAX,%RCX

  (20) 0x401e28 MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x401e32 IMUL	%RCX

  (20) 0x401e35 SAR	$0x3f,%RCX

  (20) 0x401e39 MOV	%RDX,%RAX

  (20) 0x401e3c SAR	$0x7,%RAX

  (20) 0x401e40 SUB	%RCX,%RAX

  (20) 0x401e43 ADD	%RAX,-0x2788(%RBP)

  (20) 0x401e4a CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401e4f MOV	-0x2858(%RBP),%R9

  (20) 0x401e56 MOV	%RAX,-0x2798(%RBP)

  (20) 0x401e5d MOV	-0x2850(%RBP),%R8

  (20) 0x401e64 XOR	%ESI,%ESI

  (20) 0x401e66 XOR	%EDX,%EDX

  (20) 0x401e68 VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x401e6c NOPL	(%RAX)

    (10) 0x401e70 XOR	%R10D,%R10D

    (10) 0x401e73 NOPW	%CS:(%RAX,%RAX,1)

    (10) 0x401e7e XCHG	%AX,%AX

      (9) 0x401e80 MOV	%R10D,%ECX

      (9) 0x401e83 VXORPD	%XMM4,%XMM4,%XMM4

      (9) 0x401e87 XOR	%EAX,%EAX

      (9) 0x401e89 NOPW	%CS:(%RAX,%RAX,1)

      (9) 0x401e94 NOPW	%CS:(%RAX,%RAX,1)

      (9) 0x401e9f NOPW	%CS:(%RAX,%RAX,1)

      (9) 0x401eaa NOPW	%CS:(%RAX,%RAX,1)

      (9) 0x401eb5 NOPW	%CS:(%RAX,%RAX,1)

        (8) 0x401ec0 LEA	(%RAX,%RSI,1),%EDI

        (8) 0x401ec3 INC	%EAX

        (8) 0x401ec5 VCVTSS2SD	(%RBX,%RDI,4),%XMM1,%XMM0

        (8) 0x401eca MOV	%ECX,%EDI

        (8) 0x401ecc ADD	%R8D,%ECX

        (8) 0x401ecf VCVTSS2SD	(%R15,%RDI,4),%XMM1,%XMM2

        (8) 0x401ed5 VMULSD	%XMM2,%XMM0,%XMM0

        (8) 0x401ed9 VADDSD	%XMM0,%XMM4,%XMM4

        (8) 0x401edd CMP	%R8D,%EAX

        (8) 0x401ee0 JB	401ec0

      (9) 0x401ee2 VCVTSD2SS	%XMM4,%XMM4,%XMM4

      (9) 0x401ee6 LEA	(%R10,%RSI,1),%EAX

      (9) 0x401eea INC	%R10D

      (9) 0x401eed VMOVSS	%XMM4,(%R13,%RAX,4)

      (9) 0x401ef4 CMP	%R8D,%R10D

      (9) 0x401ef7 JB	401e80

    (10) 0x401ef9 INC	%EDX

    (10) 0x401efb ADD	%R8D,%ESI

    (10) 0x401efe CMP	%R9D,%EDX

    (10) 0x401f01 JB	401e70

  (20) 0x401f07 MOV	%R9,-0x2860(%RBP)

  (20) 0x401f0e MOV	%R8,-0x2848(%RBP)

  (20) 0x401f15 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401f1a VMOVSS	0x22ee(%RIP),%XMM3

  (20) 0x401f22 MOV	-0x2848(%RBP),%R8

  (20) 0x401f29 SUB	-0x2798(%RBP),%RAX

  (20) 0x401f30 VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x401f34 VCVTSI2SS	%R8D,%XMM1,%XMM0

  (20) 0x401f39 VSQRTSS	%XMM0,%XMM0,%XMM0

  (20) 0x401f3d VDIVSS	%XMM0,%XMM3,%XMM3

  (20) 0x401f41 MOV	%RAX,%RCX

  (20) 0x401f44 MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x401f4e MOV	%R8,-0x2858(%RBP)

  (20) 0x401f55 IMUL	%RCX

  (20) 0x401f58 SAR	$0x3f,%RCX

  (20) 0x401f5c MOV	%RDX,%RAX

  (20) 0x401f5f SAR	$0x7,%RAX

  (20) 0x401f63 SUB	%RCX,%RAX

  (20) 0x401f66 ADD	%RAX,-0x2780(%RBP)

  (20) 0x401f6d VMOVSS	%XMM3,-0x2850(%RBP)

  (20) 0x401f75 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x401f7a VMOVSS	-0x2850(%RBP),%XMM3

  (20) 0x401f82 MOV	%RBX,-0x2848(%RBP)

  (20) 0x401f89 MOV	%RAX,-0x2798(%RBP)

  (20) 0x401f90 MOV	-0x27d8(%RBP),%RDI

  (20) 0x401f97 MOV	-0x27d0(%RBP),%RCX

  (20) 0x401f9e XOR	%ESI,%ESI

  (20) 0x401fa0 MOV	-0x2804(%RBP),%R11D

  (20) 0x401fa7 MOV	-0x2838(%RBP),%RBX

  (20) 0x401fae MOV	-0x27e0(%RBP),%R10

  (20) 0x401fb5 MOV	-0x2860(%RBP),%R9

  (20) 0x401fbc MOV	-0x2858(%RBP),%R8

  (20) 0x401fc3 NOPW	%CS:(%RAX,%RAX,1)

  (20) 0x401fce XCHG	%AX,%AX

    (12) 0x401fd0 MOV	%RDI,%RDX

    (12) 0x401fd3 XOR	%EAX,%EAX

    (12) 0x401fd5 NOPW	%CS:(%RAX,%RAX,1)

      (11) 0x401fe0 VMOVSS	(%RCX,%RAX,4),%XMM0

      (11) 0x401fe5 INC	%RAX

      (11) 0x401fe8 VMOVSS	%XMM0,(%RDX)

      (11) 0x401fec ADD	%R10,%RDX

      (11) 0x401fef CMP	%EAX,%R8D

      (11) 0x401ff2 JG	401fe0

    (12) 0x401ff4 INC	%ESI

    (12) 0x401ff6 ADD	$0x4,%RDI

    (12) 0x401ffa ADD	%RBX,%RCX

    (12) 0x401ffd CMP	%R11D,%ESI

    (12) 0x402000 JL	401fd0

  (20) 0x402002 MOV	-0x2848(%RBP),%RBX

  (20) 0x402009 MOV	%R9,-0x2860(%RBP)

  (20) 0x402010 MOV	%R8,-0x2858(%RBP)

  (20) 0x402017 VMOVSS	%XMM3,-0x2868(%RBP)

  (20) 0x40201f CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x402024 SUB	-0x2798(%RBP),%RAX

  (20) 0x40202b MOV	%RAX,%RCX

  (20) 0x40202e MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x402038 IMUL	%RCX

  (20) 0x40203b SAR	$0x3f,%RCX

  (20) 0x40203f MOV	%RDX,%RAX

  (20) 0x402042 SAR	$0x7,%RAX

  (20) 0x402046 SUB	%RCX,%RAX

  (20) 0x402049 ADD	%RAX,-0x2778(%RBP)

  (20) 0x402050 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x402055 VMOVSS	-0x2868(%RBP),%XMM3

  (20) 0x40205d MOV	%RBX,%RSI

  (20) 0x402060 MOV	%RAX,-0x2798(%RBP)

  (20) 0x402067 MOV	-0x27d8(%RBP),%R10

  (20) 0x40206e MOV	%R14,-0x2848(%RBP)

  (20) 0x402075 MOV	%R15,-0x2850(%RBP)

  (20) 0x40207c MOV	-0x2860(%RBP),%R9

  (20) 0x402083 MOV	-0x2858(%RBP),%R8

  (20) 0x40208a XOR	%ECX,%ECX

  (20) 0x40208c MOV	-0x27b8(%RBP),%RBX

  (20) 0x402093 XOR	%EDI,%EDI

  (20) 0x402095 XOR	%EDX,%EDX

  (20) 0x402097 VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x40209b NOPL	(%RAX,%RAX,1)

    (15) 0x4020a0 MOV	%R13,%R14

    (15) 0x4020a3 MOV	%EDX,%R13D

    (15) 0x4020a6 XOR	%EDX,%EDX

    (15) 0x4020a8 NOPL	(%RAX,%RAX,1)

      (14) 0x4020b0 MOV	%R14,%R15

      (14) 0x4020b3 MOV	%EDX,%R11D

      (14) 0x4020b6 VXORPD	%XMM4,%XMM4,%XMM4

      (14) 0x4020ba XOR	%EAX,%EAX

      (14) 0x4020bc MOV	%EDX,%R14D

      (14) 0x4020bf NOP

        (13) 0x4020c0 LEA	(%RCX,%RAX,1),%EDX

        (13) 0x4020c3 INC	%EAX

        (13) 0x4020c5 VCVTSS2SD	(%R12,%RDX,4),%XMM1,%XMM0

        (13) 0x4020cb MOV	%R11D,%EDX

        (13) 0x4020ce ADD	%R9D,%R11D

        (13) 0x4020d1 VCVTSS2SD	(%R10,%RDX,4),%XMM1,%XMM2

        (13) 0x4020d7 VMULSD	%XMM2,%XMM0,%XMM0

        (13) 0x4020db VADDSD	%XMM0,%XMM4,%XMM4

        (13) 0x4020df CMP	%R8D,%EAX

        (13) 0x4020e2 JB	4020c0

      (14) 0x4020e4 VCVTSD2SS	%XMM4,%XMM4,%XMM4

      (14) 0x4020e8 LEA	(%R14,%RDI,1),%EAX

      (14) 0x4020ec LEA	0x1(%R14),%EDX

      (14) 0x4020f0 MOV	%R15,%R14

      (14) 0x4020f3 VMULSS	%XMM3,%XMM4,%XMM4

      (14) 0x4020f7 VMOVSS	%XMM4,(%RBX,%RAX,4)

      (14) 0x4020fc CMP	%R9D,%EDX

      (14) 0x4020ff JB	4020b0

    (15) 0x402101 LEA	0x1(%R13),%EDX

    (15) 0x402105 ADD	%R9D,%EDI

    (15) 0x402108 MOV	%R15,%R13

    (15) 0x40210b ADD	%R8D,%ECX

    (15) 0x40210e CMP	%R9D,%EDX

    (15) 0x402111 JB	4020a0

  (20) 0x402113 MOV	%R9,-0x2858(%RBP)

  (20) 0x40211a MOV	-0x2850(%RBP),%R15

  (20) 0x402121 MOV	%RSI,%RBX

  (20) 0x402124 MOV	%R8,-0x2850(%RBP)

  (20) 0x40212b MOV	-0x2848(%RBP),%R14

  (20) 0x402132 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x402137 SUB	-0x2798(%RBP),%RAX

  (20) 0x40213e MOV	%RAX,%RCX

  (20) 0x402141 MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x40214b IMUL	%RCX

  (20) 0x40214e SAR	$0x3f,%RCX

  (20) 0x402152 MOV	%RDX,%RAX

  (20) 0x402155 SAR	$0x7,%RAX

  (20) 0x402159 SUB	%RCX,%RAX

  (20) 0x40215c ADD	%RAX,-0x2770(%RBP)

  (20) 0x402163 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x402168 MOV	-0x27b8(%RBP),%RDI

  (20) 0x40216f MOV	-0x2804(%RBP),%ECX

  (20) 0x402175 MOV	-0x27c0(%RBP),%RSI

  (20) 0x40217c MOV	%R14,%RDX

  (20) 0x40217f MOV	%RAX,-0x2798(%RBP)

  (20) 0x402186 CALL	402af0 <_Z7softmaxPKfPfS1_i>

  (20) 0x40218b CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x402190 SUB	-0x2798(%RBP),%RAX

  (20) 0x402197 MOV	%RAX,%RCX

  (20) 0x40219a MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x4021a4 IMUL	%RCX

  (20) 0x4021a7 SAR	$0x3f,%RCX

  (20) 0x4021ab MOV	%RDX,%RAX

  (20) 0x4021ae SAR	$0x7,%RAX

  (20) 0x4021b2 SUB	%RCX,%RAX

  (20) 0x4021b5 ADD	%RAX,-0x2768(%RBP)

  (20) 0x4021bc CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x4021c1 MOV	%R15,-0x2848(%RBP)

  (20) 0x4021c8 MOV	%RAX,-0x2798(%RBP)

  (20) 0x4021cf MOV	-0x2858(%RBP),%R9

  (20) 0x4021d6 MOV	-0x2850(%RBP),%R8

  (20) 0x4021dd XOR	%ECX,%ECX

  (20) 0x4021df MOV	-0x27f0(%RBP),%R11

  (20) 0x4021e6 XOR	%EDI,%EDI

  (20) 0x4021e8 XOR	%EDX,%EDX

  (20) 0x4021ea VXORPS	%XMM1,%XMM1,%XMM1

  (20) 0x4021ee XCHG	%AX,%AX

    (18) 0x4021f0 MOV	%R12,%R15

    (18) 0x4021f3 MOV	%EDX,%R12D

    (18) 0x4021f6 XOR	%EDX,%EDX

    (18) 0x4021f8 NOPL	(%RAX,%RAX,1)

      (17) 0x402200 MOV	%EDX,%ESI

      (17) 0x402202 VXORPD	%XMM3,%XMM3,%XMM3

      (17) 0x402206 XOR	%EAX,%EAX

      (17) 0x402208 NOPW	%CS:(%RAX,%RAX,1)

      (17) 0x402213 NOPW	%CS:(%RAX,%RAX,1)

      (17) 0x40221e NOPW	%CS:(%RAX,%RAX,1)

      (17) 0x402229 NOPW	%CS:(%RAX,%RAX,1)

      (17) 0x402234 NOPW	%CS:(%RAX,%RAX,1)

      (17) 0x40223f NOP

        (16) 0x402240 LEA	(%RAX,%RCX,1),%R10D

        (16) 0x402244 INC	%EAX

        (16) 0x402246 VCVTSS2SD	(%R14,%R10,4),%XMM1,%XMM0

        (16) 0x40224c MOV	%ESI,%R10D

        (16) 0x40224f ADD	%R8D,%ESI

        (16) 0x402252 VCVTSS2SD	(%R13,%R10,4),%XMM1,%XMM2

        (16) 0x402259 VMULSD	%XMM2,%XMM0,%XMM0

        (16) 0x40225d VADDSD	%XMM0,%XMM3,%XMM3

        (16) 0x402261 CMP	%R9D,%EAX

        (16) 0x402264 JB	402240

      (17) 0x402266 VCVTSD2SS	%XMM3,%XMM3,%XMM3

      (17) 0x40226a LEA	(%RDX,%RDI,1),%EAX

      (17) 0x40226d INC	%EDX

      (17) 0x40226f VMOVSS	%XMM3,(%R11,%RAX,4)

      (17) 0x402275 CMP	%R8D,%EDX

      (17) 0x402278 JB	402200

    (18) 0x40227a LEA	0x1(%R12),%EDX

    (18) 0x40227f ADD	%R8D,%EDI

    (18) 0x402282 MOV	%R15,%R12

    (18) 0x402285 ADD	%R9D,%ECX

    (18) 0x402288 CMP	%R9D,%EDX

    (18) 0x40228b JB	4021f0

  (20) 0x402291 MOV	-0x2848(%RBP),%R15

  (20) 0x402298 MOV	%R9,-0x2850(%RBP)

  (20) 0x40229f MOV	%R8,-0x2848(%RBP)

  (20) 0x4022a6 CALL	4010c0 <_ZNSt6chrono3_V212steady_clock3nowEv@plt>

  (20) 0x4022ab SUB	-0x2798(%RBP),%RAX

  (20) 0x4022b2 MOV	-0x27f8(%RBP),%RSI

  (20) 0x4022b9 MOV	-0x2848(%RBP),%R8

  (20) 0x4022c0 MOV	-0x2850(%RBP),%R9

  (20) 0x4022c7 MOV	%RAX,%RCX

  (20) 0x4022ca MOV	$0x20c49ba5e353f7cf,%RAX

  (20) 0x4022d4 IMUL	%RCX

  (20) 0x4022d7 SAR	$0x3f,%RCX

  (20) 0x4022db MOV	%RDX,%RAX

  (20) 0x4022de SAR	$0x7,%RAX

  (20) 0x4022e2 SUB	%RCX,%RAX

  (20) 0x4022e5 ADD	%RAX,-0x2760(%RBP)

  (20) 0x4022ec CMP	%RSI,-0x2840(%RBP)

  (20) 0x4022f3 JE	40250e

  (20) 0x4022f9 LEA	-0x2750(%RBP),%RDI

  (20) 0x402300 MOV	%R8,-0x2848(%RBP)

  (20) 0x402307 MOV	%R9,-0x2798(%RBP)

  (20) 0x40230e CALL	401050 <_ZNSt13random_device7_M_finiEv@plt>

  (20) 0x402313 MOV	-0x27e0(%RBP),%RSI

  (20) 0x40231a MOV	-0x27c0(%RBP),%RDI

  (20) 0x402321 CALL	401090 <_ZdlPvm@plt>

  (20) 0x402326 MOV	-0x27b0(%RBP),%RSI

  (20) 0x40232d MOV	%R14,%RDI

  (20) 0x402330 CALL	401090 <_ZdlPvm@plt>

  (20) 0x402335 MOV	-0x27b0(%RBP),%RSI

  (20) 0x40233c MOV	-0x27b8(%RBP),%RDI

  (20) 0x402343 CALL	401090 <_ZdlPvm@plt>

  (20) 0x402348 MOV	-0x27a0(%RBP),%RSI

  (20) 0x40234f MOV	%R13,%RDI

  (20) 0x402352 CALL	401090 <_ZdlPvm@plt>

  (20) 0x402357 MOV	-0x27a0(%RBP),%RSI

  (20) 0x40235e MOV	-0x27d8(%RBP),%RDI

  (20) 0x402365 CALL	401090 <_ZdlPvm@plt>

  (20) 0x40236a MOV	-0x27a0(%RBP),%RSI

  (20) 0x402371 MOV	-0x27d0(%RBP),%RDI

  (20) 0x402378 CALL	401090 <_ZdlPvm@plt>

  (20) 0x40237d MOV	-0x27a0(%RBP),%RSI

  (20) 0x402384 MOV	%R12,%RDI

  (20) 0x402387 CALL	401090 <_ZdlPvm@plt>

  (20) 0x40238c MOV	-0x27a0(%RBP),%RSI

  (20) 0x402393 MOV	-0x27f0(%RBP),%RDI

  (20) 0x40239a CALL	401090 <_ZdlPvm@plt>

  (20) 0x40239f MOV	-0x27a8(%RBP),%RSI

  (20) 0x4023a6 MOV	%R15,%RDI

  (20) 0x4023a9 CALL	401090 <_ZdlPvm@plt>

  (20) 0x4023ae MOV	-0x27a8(%RBP),%RSI

  (20) 0x4023b5 MOV	-0x27c8(%RBP),%RDI

  (20) 0x4023bc CALL	401090 <_ZdlPvm@plt>

  (20) 0x4023c1 MOV	-0x27a8(%RBP),%RSI

  (20) 0x4023c8 MOV	-0x27e8(%RBP),%RDI

  (20) 0x4023cf CALL	401090 <_ZdlPvm@plt>

  (20) 0x4023d4 MOV	-0x27a0(%RBP),%RSI

  (20) 0x4023db MOV	%RBX,%RDI

  (20) 0x4023de CALL	401090 <_ZdlPvm@plt>

  (20) 0x4023e3 INCQ	-0x27f8(%RBP)

  (20) 0x4023ea MOV	-0x2830(%RBP),%RBX

  (20) 0x4023f1 CMP	%RBX,-0x27f8(%RBP)

  (20) 0x4023f8 JE	4026c4

  (20) 0x4023fe MOV	-0x27a0(%RBP),%RDI

  (20) 0x402405 CALL	401080 <_Znwm@plt>

  (20) 0x40240a MOV	-0x2798(%RBP),%R9

  (20) 0x402411 MOV	-0x2848(%RBP),%R8

  (20) 0x402418 MOVL	$0,(%RAX)

  (20) 0x40241e MOV	%RAX,%RBX

  (20) 0x402421 MOV	-0x2800(%RBP),%RAX

  (20) 0x402428 DEC	%RAX

  (20) 0x40242b JNE	401493

  (20) 0x402431 JMP	4014ed

  (20) 0x402436 MOV	$0x4,%EDI

  (20) 0x40243b MOV	%R8,-0x27c0(%RBP)

  (20) 0x402442 MOV	%R9,-0x2798(%RBP)

  (20) 0x402449 CALL	401080 <_Znwm@plt>

  (20) 0x40244e MOVL	$0,(%RAX)

  (20) 0x402454 MOV	-0x27c0(%RBP),%R8

  (20) 0x40245b MOV	-0x2798(%RBP),%R9

  (20) 0x402462 MOV	%RAX,%R14

  (20) 0x402465 JMP	40174e

  (20) 0x40246a MOV	$0x4,%EDI

  (20) 0x40246f CALL	401080 <_Znwm@plt>

  (20) 0x402474 MOVL	$0,(%RAX)

  (20) 0x40247a MOV	$0x4,%EDI

  (20) 0x40247f MOV	%RAX,%R12

  (20) 0x402482 CALL	401080 <_Znwm@plt>

  (20) 0x402487 MOVL	$0,(%RAX)

  (20) 0x40248d MOV	$0x4,%EDI

  (20) 0x402492 MOV	%RAX,-0x27d0(%RBP)

  (20) 0x402499 CALL	401080 <_Znwm@plt>

  (20) 0x40249e MOVL	$0,(%RAX)

  (20) 0x4024a4 MOV	$0x4,%EDI

  (20) 0x4024a9 MOV	%RAX,-0x27d8(%RBP)

  (20) 0x4024b0 CALL	401080 <_Znwm@plt>

  (20) 0x4024b5 MOV	-0x2798(%RBP),%R9

  (20) 0x4024bc MOV	-0x27b8(%RBP),%R8

  (20) 0x4024c3 MOVL	$0,(%RAX)

  (20) 0x4024c9 MOV	%RAX,%R13

  (20) 0x4024cc JMP	401698

  (20) 0x4024d1 MOV	$0x4,%EDI

  (20) 0x4024d6 CALL	401080 <_Znwm@plt>

  (20) 0x4024db MOVL	$0,(%RAX)

  (20) 0x4024e1 MOV	$0x4,%EDI

  (20) 0x4024e6 MOV	%RAX,-0x27c8(%RBP)

  (20) 0x4024ed CALL	401080 <_Znwm@plt>

  (20) 0x4024f2 MOVL	$0,(%RAX)

  (20) 0x4024f8 MOV	-0x2798(%RBP),%R9

  (20) 0x4024ff MOV	-0x27b8(%RBP),%R8

  (20) 0x402506 MOV	%RAX,%R15

  (20) 0x402509 JMP	401598

  (20) 0x40250e VMOVSS	0x1cfe(%RIP),%XMM0

  (20) 0x402516 MOV	-0x2804(%RBP),%ECX

  (20) 0x40251c MOV	-0x27c0(%RBP),%RDX

  (20) 0x402523 MOV	-0x27b8(%RBP),%RDI

  (20) 0x40252a MOV	%R14,%RSI

  (20) 0x40252d MOV	%R8,-0x2850(%RBP)

  (20) 0x402534 MOV	%R9,-0x2848(%RBP)

  (20) 0x40253b CALL	402dd0 <_Z15ValidateSoftmaxPKfS0_S0_if>

  (20) 0x402540 MOV	$0x4041b9,%ESI

  (20) 0x402545 MOV	$0x4060c0,%EDI

  (20) 0x40254a MOV	%AL,-0x2798(%RBP)

  (20) 0x402550 CALL	401070 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>

  (20) 0x402555 MOV	$0x1b,%EDX

  (20) 0x40255a MOV	$0x4041ce,%ESI

  (20) 0x40255f MOV	$0x4060c0,%EDI

  (20) 0x402564 CALL	4010a0 <_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@plt>

  (20) 0x402569 CMPB	$0,-0x2798(%RBP)

  (20) 0x402570 MOV	$0x4040f1,%EAX

  (20) 0x402575 MOV	$0x4040ee,%ESI

  (20) 0x40257a MOV	$0x4060c0,%EDI

  (20) 0x40257f CMOVE	%RAX,%RSI

  (20) 0x402583 CALL	401070 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>

  (20) 0x402588 MOV	$0x4040ec,%ESI

  (20) 0x40258d MOV	%RAX,%RDI

  (20) 0x402590 CALL	401070 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>

  (20) 0x402595 MOV	$0x15,%EDX

  (20) 0x40259a MOV	$0x4041ea,%ESI

  (20) 0x40259f MOV	$0x4060c0,%EDI

  (20) 0x4025a4 CALL	4010a0 <_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@plt>

  (20) 0x4025a9 MOV	$0x404200,%ESI

  (20) 0x4025ae MOV	$0x4060c0,%EDI

  (20) 0x4025b3 CALL	401070 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>

  (20) 0x4025b8 MOV	$0x4040ec,%ESI

  (20) 0x4025bd MOV	%RAX,%RDI

  (20) 0x4025c0 CALL	401070 <_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@plt>

  (20) 0x4025c5 CMPB	$0,-0x2798(%RBP)

  (20) 0x4025cc MOV	-0x2848(%RBP),%R9

  (20) 0x4025d3 MOV	-0x2850(%RBP),%R8

  (20) 0x4025da JNE	4022f9

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.h: 248 - 1782

--------------------------------------------------------------------------------

248: 	    __res %= __m;

[...]

1760:     random_device() { _M_init("default"); }

[...]

1766:     { _M_fini(); }

[...]

1782:     { return this->_M_getval(); }

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/ostream.h: 739 - 739

--------------------------------------------------------------------------------

739: 	__ostream_insert(__out, __s,

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/cmath: 450 - 450

--------------------------------------------------------------------------------

450:   { return __builtin_sqrtf(__x); }

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/chrono.h: 218 - 720

--------------------------------------------------------------------------------

218: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

631: 	  __r += __d.count();

[...]

720: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/basic_string.h: 205 - 305

--------------------------------------------------------------------------------

205: 	: allocator_type(__a), _M_p(__dat) { }

[...]

234:       { _M_string_length = __length; }

235:

236:       _GLIBCXX20_CONSTEXPR

237:       pointer

238:       _M_data() const

239:       { return _M_dataplus._M_p; }

[...]

254:       _M_local_data() const

[...]

280: 	if (_M_data() == _M_local_data())

[...]

305:       { _Alloc_traits::deallocate(_M_get_allocator(), _M_data(), __size + 1); }

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc: 326 - 3374

--------------------------------------------------------------------------------

326:     mersenne_twister_engine<_UIntType, __w, __n, __m, __r, __a, __u, __d,

327: 			    __s, __b, __t, __c, __l, __f>::

328:     seed(result_type __sd)

329:     {

330:       _M_x[0] = __detail::__mod<_UIntType,

331: 	__detail::_Shift<_UIntType, __w>::__value>(__sd);

332:

333:       for (size_t __i = 1; __i < state_size; ++__i)

334: 	{

335: 	  _UIntType __x = _M_x[__i - 1];

336: 	  __x ^= __x >> (__w - 2);

337: 	  __x *= __f;

338: 	  __x += __detail::__mod<_UIntType, __n>(__i);

339: 	  _M_x[__i] = __detail::__mod<_UIntType,

340: 	    __detail::_Shift<_UIntType, __w>::__value>(__x);

341: 	}

342:       _M_p = state_size;

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

3372: 	{

3373: #if _GLIBCXX_USE_C99_MATH_FUNCS

3374: 	  __ret = std::nextafter(_RealType(1), _RealType(0));

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_construct.h: 133 - 133

--------------------------------------------------------------------------------

133:       ::new(static_cast<void*>(__p)) _Tp(std::forward<_Args>(__args)...);

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/char_traits.h: 352 - 429

--------------------------------------------------------------------------------

352: 	__c1 = __c2;

[...]

429: 	return static_cast<char_type*>(__builtin_memcpy(__s1, __s2, __n));

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 317

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

144:    for (size_t r = 0; r < rept; r++) {

[...]

160:       std::mt19937 rng(rd());

161:       std::uniform_real_distribution<float> dist(0.0f, 1.0f);

162:

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

[...]

175:       start = std::chrono::steady_clock::now();

176: #endif

177:

178:       MatMul(h_X.data(), h_WQ.data(), h_Q.data(), context_size, dim, dim);

[...]

185:       end = std::chrono::steady_clock::now();

[...]

194:       start = std::chrono::steady_clock::now();

[...]

204:       end = std::chrono::steady_clock::now();

[...]

213:       start = std::chrono::steady_clock::now();

[...]

223:       end = std::chrono::steady_clock::now();

224:       elapsed[2] += std::chrono::duration_cast<std::chrono::microseconds>(end - start);

225: #endif

226:       float scale = 1.0f / std::sqrt(static_cast<float>(dim));

[...]

233:       start = std::chrono::steady_clock::now();

234: #endif

235:

236:       for (int i = 0; i < context_size; ++i)

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

[...]

245:       end = std::chrono::steady_clock::now();

[...]

254:       start = std::chrono::steady_clock::now();

[...]

264:       end = std::chrono::steady_clock::now();

[...]

273:       start = std::chrono::steady_clock::now();

274: #endif

275:

276:       softmax(h_S.data(), h_D.data(), h_P.data(), context_size);

[...]

283:       end = std::chrono::steady_clock::now();

[...]

292:       start = std::chrono::steady_clock::now();

[...]

302:       end = std::chrono::steady_clock::now();

303:       elapsed[6] += std::chrono::duration_cast<std::chrono::microseconds>(end - start);

304: #endif

305:

306:       if (r == rept - 1) {

307:          bool softmax_ok = ValidateSoftmax(h_S.data(), h_P.data(), h_D.data(), context_size);

308:

309:          std::cout << "Validation results:\n";

310:          std::cout << "  Softmax (rows sum & D) : " << (softmax_ok ? "OK" : "FAILED") << "\n";

[...]

316:          std::cout << "  Output all finite: " << (all_finite ? "YES" : "NO") << "\n";

317:          if (!(softmax_ok && all_finite)) return 1;

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_vector.h: 2209 - 2209

--------------------------------------------------------------------------------

2209: 	if (__n > _S_max_size(_Tp_alloc_type(__a)))

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_uninitialized.h: 895 - 895

--------------------------------------------------------------------------------

895: 	      ++__first;

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_algobase.h: 925 - 1143

--------------------------------------------------------------------------------

925: 	*__first = __val;

[...]

1137:     __fill_n_a(_OutputIterator __first, _Size __n, const _Tp& __value,

[...]

1143:       if (__n <= 0)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:306-306,stl_vector.h:2209-2209,stl_uninitialized.h:895-895,stl_algobase.h:925-925
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.22
Front-end cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	5.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:306-306,stl_vector.h:2209-2209,stl_uninitialized.h:895-895,stl_algobase.h:925-925
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.22
Front-end cycles	2.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	5.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.00
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	stl_algobase.h:925-1143
Module	attention-gcc-znver5-512

The loop is defined in:

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.h:248,1760,1766,1782
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/ostream.h:739
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/cmath:450
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/chrono.h:218,631,720
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/basic_string.h:205,234-239,254,280,305
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:326-342,458-466,3367-3374
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_construct.h:133
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/char_traits.h:352,429
/home/eoseret/llm-attention/attention_v2.cpp:26-33,144,160-167,175-178,185,194,204,213,223-226,233-238,245,254,264,273-276,283,292,302-310,316-317
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_vector.h:2209
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_uninitialized.h:895
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_algobase.h:925,1137,1143

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.22 cycles (9.14x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.00 cycles (2.00x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	16
nb uops	16
loop length	90
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.00
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.00 cycles (2.00x speedup).

ASM code

In the binary file, the address of the loop is: 4014c5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x27a0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x4(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R8,-0x27b8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x2798(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x4(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 401040 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x2798(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x27b8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV $0x1fffffffffffffff,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP -0x2810(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 4012c5 <main.cold+0x145>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV -0x2820(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DEC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTQ																				scal (12.5%)
MOV %RAX,-0x2840(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)

Function	main
Source file and lines	stl_algobase.h:925-1143
Module	attention-gcc-znver5-512

The loop is defined in:

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.h:248,1760,1766,1782
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/ostream.h:739
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/cmath:450
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/new_allocator.h:151,172
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/chrono.h:218,631,720
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/basic_string.h:205,234-239,254,280,305
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:326-342,458-466,3367-3374
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_construct.h:133
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/char_traits.h:352,429
/home/eoseret/llm-attention/attention_v2.cpp:26-33,144,160-167,175-178,185,194,204,213,223-226,233-238,245,254,264,273-276,283,292,302-310,316-317
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_vector.h:2209
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_uninitialized.h:895
/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_algobase.h:925,1137,1143

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.00 cycles (2.00x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	16
nb uops	16
loop length	90
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.00
Dispatch	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4014c5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x27a0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x4(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R8,-0x27b8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x2798(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x4(%RAX),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 401040 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x2798(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x27b8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV $0x1fffffffffffffff,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP -0x2810(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JB 4012c5 <main.cold+0x145>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV -0x2820(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DEC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CLTQ																				scal (12.5%)
MOV %RAX,-0x2840(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code