OV - attention-gcc-znver5-512 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-znver5-512	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 5.01% \| (excl. loops): 0.00%

/home/eoseret/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x402af0 TEST	%ECX,%ECX

0x402af2 JLE	402dc6

0x402af8 LEA	0x8(%RSP),%R10

0x402afd AND	$-0x40,%RSP

0x402b01 MOVSXD	%ECX,%R9

0x402b04 PUSHQ	-0x8(%R10)

0x402b08 PUSH	%RBP

0x402b09 LEA	0x4(,%R9,4),%RAX

0x402b11 MOV	%RSP,%RBP

0x402b14 PUSH	%R15

0x402b16 PUSH	%R14

0x402b18 PUSH	%R13

0x402b1a PUSH	%R12

0x402b1c PUSH	%R10

0x402b1e PUSH	%RBX

0x402b1f XOR	%R15D,%R15D

0x402b22 ADD	$-0x80,%RSP

0x402b26 MOV	%RAX,-0x78(%RBP)

0x402b2a LEA	0x4(%RDX),%RAX

0x402b2e MOV	%ECX,-0x54(%RBP)

0x402b31 MOV	%RAX,-0x50(%RBP)

0x402b35 LEA	(,%R9,4),%RAX

0x402b3d MOV	%RSI,-0x68(%RBP)

0x402b41 MOVQ	$0,-0x48(%RBP)

0x402b49 MOV	%RAX,-0x70(%RBP)

0x402b4d MOVQ	$0x1,-0x40(%RBP)

0x402b55 MOV	%R9,-0x80(%RBP)

0x402b59 MOV	%RDI,-0x88(%RBP)

0x402b60 MOV	%RDX,-0x60(%RBP)

0x402b64 MOV	%RDI,%R14

0x402b67 LEA	0x4(%RDI),%RBX

0x402b6b CMP	$0xe,%R15D

0x402b6f JLE	402d84

0x402b75 NOPW	%CS:(%RAX,%RAX,1)

    (30) 0x402b80 MOV	-0x40(%RBP),%ESI

    (30) 0x402b83 VBROADCASTSS	0x1677(%RIP),%ZMM0

    (30) 0x402b8d MOV	-0x40(%RBP),%EDI

    (30) 0x402b90 MOV	%R14,%RAX

    (30) 0x402b93 SHR	$0x4,%ESI

    (30) 0x402b96 SAL	$0x6,%RSI

    (30) 0x402b9a ADD	%R14,%RSI

    (30) 0x402b9d NOPL	(%RAX)

      (29) 0x402ba0 VMAXPS	(%RAX),%ZMM0,%ZMM0

      (29) 0x402ba6 ADD	$0x40,%RAX

      (29) 0x402baa CMP	%RAX,%RSI

      (29) 0x402bad JNE	402ba0

    (30) 0x402baf VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

    (30) 0x402bb6 VMOVAPS	%YMM0,%YMM1

    (30) 0x402bba VMAXPS	%YMM0,%YMM3,%YMM2

    (30) 0x402bbe VEXTRACTF32X4	$0x1,%YMM2,%XMM0

    (30) 0x402bc5 VMAXPS	%XMM2,%XMM0,%XMM0

    (30) 0x402bc9 VMOVHLPS	%XMM0,%XMM0,%XMM2

    (30) 0x402bcd VMAXPS	%XMM0,%XMM2,%XMM2

    (30) 0x402bd1 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

    (30) 0x402bd6 VMAXPS	%XMM2,%XMM0,%XMM0

    (30) 0x402bda TEST	$0xf,%DIL

    (30) 0x402bde JE	402c9a

  (31) 0x402be4 MOV	%EDI,%EAX

  (31) 0x402be6 VMAXPS	%YMM3,%YMM1,%YMM1

  (31) 0x402bea AND	$-0x10,%EAX

  (31) 0x402bed MOV	%EAX,%ESI

  (31) 0x402bef MOV	%R15D,%EDI

  (31) 0x402bf2 SUB	%EAX,%EDI

  (31) 0x402bf4 CMP	$0x6,%EDI

  (31) 0x402bf7 JBE	402c32

  (31) 0x402bf9 ADD	-0x48(%RBP),%RAX

  (31) 0x402bfd MOV	-0x88(%RBP),%RCX

  (31) 0x402c04 INC	%EDI

  (31) 0x402c06 VMAXPS	(%RCX,%RAX,4),%YMM1,%YMM0

  (31) 0x402c0b VEXTRACTF32X4	$0x1,%YMM0,%XMM1

  (31) 0x402c12 VMAXPS	%XMM0,%XMM1,%XMM0

  (31) 0x402c16 VMOVHLPS	%XMM0,%XMM0,%XMM1

  (31) 0x402c1a VMAXPS	%XMM0,%XMM1,%XMM1

  (31) 0x402c1e VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

  (31) 0x402c23 VMAXPS	%XMM1,%XMM0,%XMM0

  (31) 0x402c27 TEST	$0x7,%DIL

  (31) 0x402c2b JE	402c9a

  (31) 0x402c2d AND	$-0x8,%EDI

  (31) 0x402c30 ADD	%EDI,%ESI

  (31) 0x402c32 MOVSXD	%ESI,%RDI

  (31) 0x402c35 VMAXSS	(%R14,%RDI,4),%XMM0,%XMM0

  (31) 0x402c3b LEA	(,%RDI,4),%RAX

  (31) 0x402c43 CMP	%ESI,%R15D

  (31) 0x402c46 JLE	402c9a

  (31) 0x402c48 LEA	0x2(%RSI),%EDI

  (31) 0x402c4b VMAXSS	0x4(%R14,%RAX,1),%XMM0,%XMM0

  (31) 0x402c52 CMP	%EDI,%R15D

  (31) 0x402c55 JL	402c9a

  (31) 0x402c57 LEA	0x3(%RSI),%EDI

  (31) 0x402c5a VMAXSS	0x8(%R14,%RAX,1),%XMM0,%XMM0

  (31) 0x402c61 CMP	%EDI,%R15D

  (31) 0x402c64 JL	402c9a

  (31) 0x402c66 LEA	0x4(%RSI),%EDI

  (31) 0x402c69 VMAXSS	0xc(%R14,%RAX,1),%XMM0,%XMM0

  (31) 0x402c70 CMP	%R15D,%EDI

  (31) 0x402c73 JG	402c9a

  (31) 0x402c75 LEA	0x5(%RSI),%EDI

  (31) 0x402c78 VMAXSS	0x10(%R14,%RAX,1),%XMM0,%XMM0

  (31) 0x402c7f CMP	%EDI,%R15D

  (31) 0x402c82 JL	402c9a

  (31) 0x402c84 ADD	$0x6,%ESI

  (31) 0x402c87 VMAXSS	0x14(%R14,%RAX,1),%XMM0,%XMM0

  (31) 0x402c8e CMP	%ESI,%R15D

  (31) 0x402c91 JL	402c9a

  (31) 0x402c93 VMAXSS	0x18(%R14,%RAX,1),%XMM0,%XMM0

    (30) 0x402c9a MOVL	$0,-0x34(%RBP)

    (30) 0x402ca1 VMOVSS	%XMM0,-0x38(%RBP)

    (30) 0x402ca6 MOV	%R14,%R12

    (30) 0x402ca9 VZEROUPPER

    (30) 0x402cac NOPL	(%RAX)

      (27) 0x402cb0 VMOVSS	(%R12),%XMM1

      (27) 0x402cb6 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (27) 0x402cbb ADD	$0x4,%R12

      (27) 0x402cbf CALL	401110 <expf@plt>

      (27) 0x402cc4 VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (27) 0x402cc9 VMOVSS	%XMM5,-0x34(%RBP)

      (27) 0x402cce CMP	%R12,%RBX

      (27) 0x402cd1 JNE	402cb0

    (30) 0x402cd3 MOV	-0x60(%RBP),%RAX

    (30) 0x402cd7 MOV	-0x48(%RBP),%RCX

    (30) 0x402cdb MOV	%R14,%R13

    (30) 0x402cde LEA	(%RAX,%RCX,4),%R12

    (30) 0x402ce2 NOPW	%CS:(%RAX,%RAX,1)

    (30) 0x402ced NOPL	(%RAX)

      (28) 0x402cf0 VMOVSS	(%R13),%XMM1

      (28) 0x402cf6 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (28) 0x402cfb ADD	$0x4,%R13

      (28) 0x402cff ADD	$0x4,%R12

      (28) 0x402d03 CALL	401110 <expf@plt>

      (28) 0x402d08 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (28) 0x402d0d VMOVSS	%XMM0,-0x4(%R12)

      (28) 0x402d14 CMP	%R13,%RBX

      (28) 0x402d17 JNE	402cf0

    (30) 0x402d19 MOV	-0x54(%RBP),%EDX

    (30) 0x402d1c LEA	0x1(%R15),%R8D

    (30) 0x402d20 CMP	%R8D,%EDX

    (30) 0x402d23 JE	402da0

    (30) 0x402d25 INCQ	-0x40(%RBP)

    (30) 0x402d29 MOV	-0x50(%RBP),%R13

    (30) 0x402d2d MOV	%EDX,%EAX

    (30) 0x402d2f MOV	-0x80(%RBP),%RDI

    (30) 0x402d33 MOV	-0x40(%RBP),%R15

    (30) 0x402d37 ADD	%RDI,-0x48(%RBP)

    (30) 0x402d3b XOR	%ESI,%ESI

    (30) 0x402d3d MOV	-0x78(%RBP),%R12

    (30) 0x402d41 ADD	-0x70(%RBP),%R14

    (30) 0x402d45 MOV	%R8D,-0x38(%RBP)

    (30) 0x402d49 MOV	%R13,%RDI

    (30) 0x402d4c SUB	%R15D,%EAX

    (30) 0x402d4f ADD	%R12,%R13

    (30) 0x402d52 ADD	%R12,%RBX

    (30) 0x402d55 LEA	0x4(,%RAX,4),%RDX

    (30) 0x402d5d CALL	401040 <memset@plt>

    (30) 0x402d62 VMOVSS	-0x34(%RBP),%XMM2

    (30) 0x402d67 MOV	-0x68(%RBP),%RAX

    (30) 0x402d6b MOV	%R13,-0x50(%RBP)

    (30) 0x402d6f VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

    (30) 0x402d76 MOV	-0x38(%RBP),%R15D

    (30) 0x402d7a CMP	$0xe,%R15D

    (30) 0x402d7e JG	402b80

(32) 0x402d84 VBROADCASTSS	0x1477(%RIP),%YMM1

(32) 0x402d8d VMOVSS	0x146f(%RIP),%XMM0

(32) 0x402d95 XOR	%EAX,%EAX

(32) 0x402d97 XOR	%ESI,%ESI

(32) 0x402d99 JMP	402bef

0x402d9e XCHG	%AX,%AX

0x402da0 VMOVSS	-0x34(%RBP),%XMM2

0x402da5 MOV	-0x68(%RBP),%RAX

0x402da9 MOV	%R15D,%EDX

0x402dac VMOVSS	%XMM2,(%RAX,%RDX,4)

0x402db1 SUB	$-0x80,%RSP

0x402db5 POP	%RBX

0x402db6 POP	%R10

0x402db8 POP	%R12

0x402dba POP	%R13

0x402dbc POP	%R14

0x402dbe POP	%R15

0x402dc0 POP	%RBP

0x402dc1 LEA	-0x8(%R10),%RSP

0x402dc5 RET

0x402dc6 RET

0x402dc7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-znver5-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-znver5-512

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.50 to 0.46 cycles (14.07x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	51
nb uops	52
loop length	194
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.50	0.50
cycles	2.67	2.67	2.67	2.67	2.67	2.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	3.50
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

1% of peak load performance is reached (3.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.50 to 3.50 cycles (1.86x speedup).

ASM code

In the binary file, the address of the function is: 402af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402dc6 <_Z7softmaxPKfPfS1_i+0x2d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ECX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA 0x4(,%R9,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA (,%R9,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
LEA 0x4(%RDI),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0xe,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402d84 <_Z7softmaxPKfPfS1_i+0x294>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (6.3%)
SUB $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x8(%R10),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-znver5-512

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.17 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	51
nb uops	52
loop length	194
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.50	0.50
cycles	2.67	2.67	2.67	2.67	2.67	2.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	3.50
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.50 cycles. At this rate:

1% of peak load performance is reached (3.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.31 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402af0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402dc6 <_Z7softmaxPKfPfS1_i+0x2d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ECX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LEA 0x4(,%R9,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA (,%R9,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
LEA 0x4(%RDI),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP $0xe,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402d84 <_Z7softmaxPKfPfS1_i+0x294>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (6.3%)
SUB $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x8(%R10),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	5.01	0.34
▼Loop 32 - attention_v2.cpp:43-61 - attention-gcc-znver5-512–	0.00	0.00
▼Loop 31 - attention_v2.cpp:43-61 - attention-gcc-znver5-512–	0.07	0.00
▼Loop 30 - attention_v2.cpp:43-61 - attention-gcc-znver5-512–	0.15	0.01
○Loop 28 - attention_v2.cpp:55-56 - attention-gcc-znver5-512	3.74	0.25
○Loop 27 - attention_v2.cpp:52-53 - attention-gcc-znver5-512	1.05	0.07
○Loop 29 - attention_v2.cpp:47-48 - attention-gcc-znver5-512	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code