OV - attention-gcc-znver5-256 - Loop 30 - attention-gcc-znver5-256

	Loop Id: 30	Module: attention-gcc-znver5-256	Source: attention_v2.cpp:43-61	Coverage: 0.23%

0x402b50 LEA	0x1(%R12),%ECX

0x402b55 VBROADCASTSS	0x16a6(%RIP),%YMM0

0x402b5e MOV	%R13,%RAX

0x402b61 MOV	%ECX,%EDX

0x402b63 SHR	$0x3,%EDX

0x402b66 SAL	$0x5,%RDX

0x402b6a ADD	%R13,%RDX

0x402b6d NOPL	(%RAX)

  (29) 0x402b70 VMAXPS	(%RAX),%YMM0,%YMM0

  (29) 0x402b74 ADD	$0x20,%RAX

  (29) 0x402b78 CMP	%RAX,%RDX

  (29) 0x402b7b JNE	402b70

0x402b7d VEXTRACTF32X4	$0x1,%YMM0,%XMM1

0x402b84 VMAXPS	%XMM0,%XMM1,%XMM1

0x402b88 VMOVHLPS	%XMM1,%XMM1,%XMM0

0x402b8c VMAXPS	%XMM1,%XMM0,%XMM0

0x402b90 VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

0x402b95 VMAXPS	%XMM0,%XMM1,%XMM0

0x402b99 VMOVSS	%XMM0,-0x38(%RBP)

0x402b9e TEST	$0x7,%CL

0x402ba1 JE	402d20

0x402c40 MOVL	$0,-0x34(%RBP)

0x402c47 MOV	%R13,%R14

0x402c4a NOPW	(%RAX,%RAX,1)

  (27) 0x402c50 VMOVSS	(%R14),%XMM0

  (27) 0x402c55 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (27) 0x402c5a ADD	$0x4,%R14

  (27) 0x402c5e CALL	401110 <expf@plt>

  (27) 0x402c63 VADDSS	-0x34(%RBP),%XMM0,%XMM3

  (27) 0x402c68 VMOVSS	%XMM3,-0x34(%RBP)

  (27) 0x402c6d CMP	%R14,%RBX

  (27) 0x402c70 JNE	402c50

0x402c72 MOV	-0x40(%RBP),%R14

0x402c76 MOV	%R13,%R15

0x402c79 NOPL	(%RAX)

  (28) 0x402c80 VMOVSS	(%R15),%XMM0

  (28) 0x402c85 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (28) 0x402c8a ADD	$0x4,%R15

  (28) 0x402c8e ADD	$0x4,%R14

  (28) 0x402c92 CALL	401110 <expf@plt>

  (28) 0x402c97 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

  (28) 0x402c9c VMOVSS	%XMM0,-0x4(%R14)

  (28) 0x402ca2 CMP	%R15,%RBX

  (28) 0x402ca5 JNE	402c80

0x402ca7 CMP	-0x58(%RBP),%R12

0x402cab JE	402d30

0x402cb1 MOV	-0x68(%RBP),%RAX

0x402cb5 MOV	-0x50(%RBP),%R15

0x402cb9 XOR	%ESI,%ESI

0x402cbb MOV	-0x70(%RBP),%R14

0x402cbf ADD	%RAX,-0x40(%RBP)

0x402cc3 ADD	%RAX,%R13

0x402cc6 MOV	-0x48(%RBP),%EAX

0x402cc9 MOV	%R15,%RDI

0x402ccc ADD	%R14,%RBX

0x402ccf SUB	-0x44(%RBP),%EAX

0x402cd2 LEA	0x4(,%RAX,4),%RDX

0x402cda CALL	401040 <memset@plt>

0x402cdf VMOVSS	-0x34(%RBP),%XMM7

0x402ce4 MOV	-0x60(%RBP),%RAX

0x402ce8 VMOVSS	%XMM7,(%RAX,%R12,4)

0x402cee INC	%R12

0x402cf1 LEA	(%R15,%R14,1),%RAX

0x402cf5 MOV	%RAX,-0x50(%RBP)

0x402cf9 MOV	%R12D,-0x44(%RBP)

0x402cfd CMP	$0x6,%R12

0x402d01 JA	402b50

0x402d20 VZEROUPPER

0x402d23 JMP	402c40

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-znver5-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.13
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.13
CQA cycles if fully vectorized	0.58
Front-end cycles	6.13
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	49.00
Nb loads	11.00
Nb stores	6.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.98
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.17
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.28
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.07

Metric	Value
CQA speedup if no scalar integer	3.06
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.13
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	6.13
CQA cycles if fully vectorized	0.58
Front-end cycles	6.13
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	49.00
Nb loads	11.00
Nb stores	6.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.98
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.17
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.28
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.07

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43,46-47,50-52,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 2.00 cycles (3.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes (18 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

General properties

nb instructions	48
nb uops	49
loop length	208
used x86 registers	11
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	4.00	4.00	4.00	4.00	1.50	1.50	1.50	1.50	1.00	1.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	4.00	4.00	4.00	4.00	1.50	1.50	1.50	1.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	4.00
Overall L1	6.13

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	29%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	13%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.13 cycles. At this rate:

4% of peak load performance is reached (11.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.13 to 4.00 cycles (1.53x speedup).

ASM code

In the binary file, the address of the loop is: 402c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x1(%R12),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS 0x16a6(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1-2	0.50	scal (6.3%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x3,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
SAL $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (12.5%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSS %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
TEST $0x7,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 402d20 <_Z7softmaxPKfPfS1_i+0x250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP -0x58(%RBP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402d30 <_Z7softmaxPKfPfS1_i+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x70(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RAX,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB -0x44(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x4(,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 401040 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM7,(%RAX,%R12,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%R14,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12D,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP $0x6,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 402b50 <_Z7softmaxPKfPfS1_i+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 402c40 <_Z7softmaxPKfPfS1_i+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43,46-47,50-52,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 2.00 cycles (3.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	48
nb uops	49
loop length	208
used x86 registers	11
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	4.00	4.00	4.00	4.00	1.50	1.50	1.50	1.50	1.00	1.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	4.00	4.00	4.00	4.00	1.50	1.50	1.50	1.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	4.00
Overall L1	6.13

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	29%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	13%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.13 cycles. At this rate:

4% of peak load performance is reached (11.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 402c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA 0x1(%R12),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS 0x16a6(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1-2	0.50	scal (6.3%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x3,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
SAL $0x5,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (12.5%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSS %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
TEST $0x7,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 402d20 <_Z7softmaxPKfPfS1_i+0x250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMP -0x58(%RBP),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 402d30 <_Z7softmaxPKfPfS1_i+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x70(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RAX,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB -0x44(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
LEA 0x4(,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 401040 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS -0x34(%RBP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM7,(%RAX,%R12,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R15,%R14,1),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12D,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP $0x6,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 402b50 <_Z7softmaxPKfPfS1_i+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 402c40 <_Z7softmaxPKfPfS1_i+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code