OV - attention-gcc-znver5-256 - Loop 18 - attention-gcc-znver5-256

0x4021f0 MOV	%R12,%R15

0x4021f3 MOV	%EDX,%R12D

0x4021f6 XOR	%EDX,%EDX

0x4021f8 NOPL	(%RAX,%RAX,1)

  (17) 0x402200 MOV	%EDX,%ESI

  (17) 0x402202 VXORPD	%XMM3,%XMM3,%XMM3

  (17) 0x402206 XOR	%EAX,%EAX

  (17) 0x402208 NOPW	%CS:(%RAX,%RAX,1)

  (17) 0x402213 NOPW	%CS:(%RAX,%RAX,1)

  (17) 0x40221e NOPW	%CS:(%RAX,%RAX,1)

  (17) 0x402229 NOPW	%CS:(%RAX,%RAX,1)

  (17) 0x402234 NOPW	%CS:(%RAX,%RAX,1)

  (17) 0x40223f NOP

    (16) 0x402240 LEA	(%RAX,%RCX,1),%R10D

    (16) 0x402244 INC	%EAX

    (16) 0x402246 VCVTSS2SD	(%R14,%R10,4),%XMM1,%XMM0

    (16) 0x40224c MOV	%ESI,%R10D

    (16) 0x40224f ADD	%R8D,%ESI

    (16) 0x402252 VCVTSS2SD	(%R13,%R10,4),%XMM1,%XMM2

    (16) 0x402259 VMULSD	%XMM2,%XMM0,%XMM0

    (16) 0x40225d VADDSD	%XMM0,%XMM3,%XMM3

    (16) 0x402261 CMP	%R9D,%EAX

    (16) 0x402264 JB	402240

  (17) 0x402266 VCVTSD2SS	%XMM3,%XMM3,%XMM3

  (17) 0x40226a LEA	(%RDX,%RDI,1),%EAX

  (17) 0x40226d INC	%EDX

  (17) 0x40226f VMOVSS	%XMM3,(%R11,%RAX,4)

  (17) 0x402275 CMP	%R8D,%EDX

  (17) 0x402278 JB	402200

0x40227a LEA	0x1(%R12),%EDX

0x40227f ADD	%R8D,%EDI

0x402282 MOV	%R15,%R12

0x402285 ADD	%R9D,%ECX

0x402288 CMP	%R9D,%EDX

0x40228b JB	4021f0

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.69
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	1.13
CQA cycles if FP arith vectorized	1.13
CQA cycles if fully vectorized	0.07
Front-end cycles	1.13
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	9.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.69
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	1.13
CQA cycles if FP arith vectorized	1.13
CQA cycles if fully vectorized	0.07
Front-end cycles	1.13
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	9.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.07 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
nb uops	9
loop length	39
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Dispatch	0.67
Data deps.	1.00
Overall L1	1.13

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.13 to 0.67 cycles (1.69x speedup).

ASM code

In the binary file, the address of the loop is: 4021f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
MOV %R12,%R15	1	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0.13	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.13	N/A
LEA 0x1(%R12),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %R8D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %R15,%R12	1	0	0	0	0	0	0	0	0.13	N/A
ADD %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
CMP %R9D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
JB 4021f0 <main+0xef0>	1	0	0	0	0.33	0.33	0.33	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.07 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
nb uops	9
loop length	39
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Dispatch	0.67
Data deps.	1.00
Overall L1	1.13

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.13 to 0.67 cycles (1.69x speedup).

ASM code

In the binary file, the address of the loop is: 4021f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
MOV %R12,%R15	1	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0.13	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.13	N/A
LEA 0x1(%R12),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %R8D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %R15,%R12	1	0	0	0	0	0	0	0	0.13	N/A
ADD %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
CMP %R9D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
JB 4021f0 <main+0xef0>	1	0	0	0	0.33	0.33	0.33	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code