OV - attention-gcc-znver5-256 - Function std::mersenne_twister_engine<unsigned long, 32ul, 624ul, 397ul, 31ul, 2567483615ul, 11ul, 4294967295ul, 7ul, 2636928640ul, 15ul, 4022730752ul, 18ul, 1812433253ul>::_M_gen

	Function: std::mersenne_twister_engine<unsigned long, 32ul, 624ul, 397ul, 31ul, 2567483615ul, 11ul, ...	Module: attention-gcc-znver5-256	Source: random.tcc:397-425 [...]	Coverage (incl. loops): 0.08% \| (excl. loops): 0.08%

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc: 397 - 425

--------------------------------------------------------------------------------

397:     mersenne_twister_engine<_UIntType, __w, __n, __m, __r, __a, __u, __d,

[...]

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

424:       _M_p = 0;

425:     }

0x403200 MOV	$-0x80000000,%RDX

0x403207 LEA	0x700(%RDI),%RCX

0x40320e MOV	%RDI,%RAX

0x403211 VPBROADCASTQ	%RDX,%YMM5

0x403217 MOV	$0x7fffffff,%EDX

0x40321c VPBROADCASTQ	%RDX,%YMM4

0x403222 MOV	$0x1,%EDX

0x403227 VPBROADCASTQ	%RDX,%YMM3

0x40322d MOV	$-0x66f74f21,%EDX

0x403232 VPBROADCASTQ	%RDX,%YMM2

0x403238 NOPL	(%RAX,%RAX,1)

(37) 0x403240 VPANDQ	0x8(%RAX),%YMM4,%YMM1

(37) 0x40324a VMOVDQA	%YMM5,%YMM0

(37) 0x40324e ADD	$0x20,%RAX

(37) 0x403252 VPTERNLOGQ	$-0x14,-0x20(%RAX),%YMM1,%YMM0

(37) 0x40325a VPSRLQ	$0x1,%YMM0,%YMM1

(37) 0x40325f VPANDQ	%YMM3,%YMM0,%YMM0

(37) 0x403265 VPMULLQ	%YMM2,%YMM0,%YMM0

(37) 0x40326b VPTERNLOGQ	$-0x6a,0xc48(%RAX),%YMM0,%YMM1

(37) 0x403276 VMOVDQU	%YMM1,-0x20(%RAX)

(37) 0x40327b CMP	%RAX,%RCX

(37) 0x40327e JNE	403240

0x403280 MOV	0x708(%RDI),%RAX

0x403287 MOV	0x700(%RDI),%RDX

0x40328e MOV	%RAX,%RCX

0x403291 AND	$0x7fffffff,%ECX

0x403297 AND	$-0x80000000,%RDX

0x40329e AND	$-0x80000000,%RAX

0x4032a4 OR	%RCX,%RDX

0x4032a7 MOV	%RDX,%RCX

0x4032aa SHR	$0x1,%RCX

0x4032ad XOR	0x1368(%RDI),%RCX

0x4032b4 AND	$0x1,%EDX

0x4032b7 NEG	%RDX

0x4032ba AND	$-0x66f74f21,%EDX

0x4032c0 XOR	%RCX,%RDX

0x4032c3 MOV	0x710(%RDI),%RCX

0x4032ca MOV	%RDX,0x700(%RDI)

0x4032d1 MOV	%RCX,%RDX

0x4032d4 AND	$0x7fffffff,%EDX

0x4032da AND	$-0x80000000,%RCX

0x4032e1 OR	%RDX,%RAX

0x4032e4 MOV	%RAX,%RDX

0x4032e7 SHR	$0x1,%RDX

0x4032ea XOR	0x1370(%RDI),%RDX

0x4032f1 AND	$0x1,%EAX

0x4032f4 NEG	%RAX

0x4032f7 AND	$-0x66f74f21,%EAX

0x4032fc XOR	%RDX,%RAX

0x4032ff MOV	%RAX,0x708(%RDI)

0x403306 MOV	0x718(%RDI),%RAX

0x40330d AND	$0x7fffffff,%EAX

0x403312 OR	%RCX,%RAX

0x403315 LEA	0x1378(%RDI),%RCX

0x40331c MOV	%RAX,%RDX

0x40331f SHR	$0x1,%RDX

0x403322 XOR	0x1378(%RDI),%RDX

0x403329 AND	$0x1,%EAX

0x40332c NEG	%RAX

0x40332f AND	$-0x66f74f21,%EAX

0x403334 XOR	%RDX,%RAX

0x403337 MOV	$-0x80000000,%RDX

0x40333e VPBROADCASTQ	%RDX,%YMM5

0x403344 MOV	$0x7fffffff,%EDX

0x403349 MOV	%RAX,0x710(%RDI)

0x403350 LEA	0x718(%RDI),%RAX

0x403357 VPBROADCASTQ	%RDX,%YMM4

0x40335d MOV	$0x1,%EDX

0x403362 VPBROADCASTQ	%RDX,%YMM3

0x403368 MOV	$-0x66f74f21,%EDX

0x40336d VPBROADCASTQ	%RDX,%YMM2

0x403373 NOPW	%CS:(%RAX,%RAX,1)

0x40337e XCHG	%AX,%AX

(38) 0x403380 VPANDQ	0x8(%RAX),%YMM4,%YMM1

(38) 0x40338a VMOVDQA	%YMM5,%YMM0

(38) 0x40338e ADD	$0x20,%RAX

(38) 0x403392 VPTERNLOGQ	$-0x14,-0x20(%RAX),%YMM1,%YMM0

(38) 0x40339a VPSRLQ	$0x1,%YMM0,%YMM1

(38) 0x40339f VPANDQ	%YMM3,%YMM0,%YMM0

(38) 0x4033a5 VPMULLQ	%YMM2,%YMM0,%YMM0

(38) 0x4033ab VPTERNLOGQ	$-0x6a,-0x738(%RAX),%YMM0,%YMM1

(38) 0x4033b6 VMOVDQU	%YMM1,-0x20(%RAX)

(38) 0x4033bb CMP	%RCX,%RAX

(38) 0x4033be JNE	403380

0x4033c0 MOV	0x1378(%RDI),%RAX

0x4033c7 MOV	(%RDI),%RDX

0x4033ca MOVQ	$0,0x1380(%RDI)

0x4033d5 AND	$0x7fffffff,%EDX

0x4033db AND	$-0x80000000,%RAX

0x4033e1 OR	%RDX,%RAX

0x4033e4 MOV	%RAX,%RDX

0x4033e7 SHR	$0x1,%RDX

0x4033ea XOR	0xc60(%RDI),%RDX

0x4033f1 AND	$0x1,%EAX

0x4033f4 NEG	%RAX

0x4033f7 AND	$-0x66f74f21,%EAX

0x4033fc XOR	%RDX,%RAX

0x4033ff MOV	%RAX,0x1378(%RDI)

0x403406 VZEROUPPER

0x403409 RET

Coverage (%)	Name	Source Location	Module
○100.00	main	random.tcc:462	attention-gcc-znver5-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.08% of application time for run run_0

Source file and lines	random.tcc:397-425
Module	attention-gcc-znver5-256

The function is defined in /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:397,404-425.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.75 to 4.00 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 8 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:406
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:407
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:409
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:414
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:415
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:417
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	78
nb uops	86
loop length	394
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.00	8.00	8.00	8.00	8.00	8.00	3.75	3.75	3.75	3.75	0.00	4.00	4.00	0.00	0.00	0.00
cycles	8.00	8.00	8.00	8.00	8.00	8.00	3.75	3.75	3.75	3.75	0.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.75
Dispatch	8.00
Overall L1	10.75

Vectorization ratios

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

all	10%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.75 cycles. At this rate:

2% of peak load performance is reached (7.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.75 to 8.00 cycles (1.34x speedup).

ASM code

In the binary file, the address of the function is: 403200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
MOV $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x700(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
VPBROADCASTQ %RDX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x708(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x700(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $0x7fffffff,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x80000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1368(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x710(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RDX,0x700(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1370(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x708(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x718(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
AND $0x7fffffff,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1378(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1378(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x710(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x718(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RDX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x1378(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOVQ $0,0x1380(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
AND $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0xc60(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x1378(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.08% of application time for run run_0

Source file and lines	random.tcc:397-425
Module	attention-gcc-znver5-256

The function is defined in /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:397,404-425.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.75 to 4.00 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 8 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:406
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:407
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:409
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:414
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:415
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:417
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	78
nb uops	86
loop length	394
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.00	8.00	8.00	8.00	8.00	8.00	3.75	3.75	3.75	3.75	0.00	4.00	4.00	0.00	0.00	0.00
cycles	8.00	8.00	8.00	8.00	8.00	8.00	3.75	3.75	3.75	3.75	0.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.75
Dispatch	8.00
Overall L1	10.75

Vectorization ratios

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

all	10%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.75 cycles. At this rate:

2% of peak load performance is reached (7.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 403200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
MOV $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x700(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
VPBROADCASTQ %RDX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x708(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV 0x700(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $0x7fffffff,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x80000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1368(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x710(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV %RDX,0x700(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1370(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x708(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x718(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
AND $0x7fffffff,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1378(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1378(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x710(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x718(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RDX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
MOV $-0x66f74f21,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RDX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x1378(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOVQ $0,0x1380(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
AND $0x7fffffff,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
OR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0xc60(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
AND $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
NEG %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x1378(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼std::mersenne_twister_engine::_M_gen_rand()–	0.08	0.00
○Loop 37 - random.tcc:404-409 - attention-gcc-znver5-256	0.00	0.00
○Loop 38 - random.tcc:412-417 - attention-gcc-znver5-256	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code