OV - attention-gcc-znver5-256 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-znver5-256	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 5.78% \| (excl. loops): 0.00%

/home/eoseret/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x402ad0 TEST	%ECX,%ECX

0x402ad2 JLE	402d54

0x402ad8 LEA	0x8(%RSP),%R10

0x402add AND	$-0x20,%RSP

0x402ae1 MOVSXD	%ECX,%RAX

0x402ae4 PUSHQ	-0x8(%R10)

0x402ae8 PUSH	%RBP

0x402ae9 MOV	%RSP,%RBP

0x402aec PUSH	%R15

0x402aee PUSH	%R14

0x402af0 PUSH	%R13

0x402af2 PUSH	%R12

0x402af4 PUSH	%R10

0x402af6 PUSH	%RBX

0x402af7 XOR	%R12D,%R12D

0x402afa SUB	$0x40,%RSP

0x402afe MOV	%RSI,-0x60(%RBP)

0x402b02 LEA	0x4(,%RAX,4),%RSI

0x402b0a MOV	%RDX,-0x40(%RBP)

0x402b0e MOV	%RSI,-0x70(%RBP)

0x402b12 LEA	0x4(%RDX),%RSI

0x402b16 MOV	%R12D,-0x44(%RBP)

0x402b1a MOV	%RDI,%R13

0x402b1d MOV	%RSI,-0x50(%RBP)

0x402b21 LEA	0x4(%RDI),%RBX

0x402b25 SAL	$0x2,%RAX

0x402b29 MOV	%RAX,-0x68(%RBP)

0x402b2d LEA	-0x1(%RCX),%EAX

0x402b30 MOV	%RAX,-0x58(%RBP)

0x402b34 LEA	-0x2(%RCX),%EAX

0x402b37 MOV	%EAX,-0x48(%RBP)

0x402b3a CMP	$0x6,%R12

0x402b3e JBE	402d07

0x402b44 NOPW	%CS:(%RAX,%RAX,1)

0x402b4f NOP

    (30) 0x402b50 LEA	0x1(%R12),%ECX

    (30) 0x402b55 VBROADCASTSS	0x16a6(%RIP),%YMM0

    (30) 0x402b5e MOV	%R13,%RAX

    (30) 0x402b61 MOV	%ECX,%EDX

    (30) 0x402b63 SHR	$0x3,%EDX

    (30) 0x402b66 SAL	$0x5,%RDX

    (30) 0x402b6a ADD	%R13,%RDX

    (30) 0x402b6d NOPL	(%RAX)

      (29) 0x402b70 VMAXPS	(%RAX),%YMM0,%YMM0

      (29) 0x402b74 ADD	$0x20,%RAX

      (29) 0x402b78 CMP	%RAX,%RDX

      (29) 0x402b7b JNE	402b70

    (30) 0x402b7d VEXTRACTF32X4	$0x1,%YMM0,%XMM1

    (30) 0x402b84 VMAXPS	%XMM0,%XMM1,%XMM1

    (30) 0x402b88 VMOVHLPS	%XMM1,%XMM1,%XMM0

    (30) 0x402b8c VMAXPS	%XMM1,%XMM0,%XMM0

    (30) 0x402b90 VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

    (30) 0x402b95 VMAXPS	%XMM0,%XMM1,%XMM0

    (30) 0x402b99 VMOVSS	%XMM0,-0x38(%RBP)

    (30) 0x402b9e TEST	$0x7,%CL

    (30) 0x402ba1 JE	402d20

  (31) 0x402ba7 MOV	%ECX,%EAX

  (31) 0x402ba9 AND	$-0x8,%EAX

  (31) 0x402bac VZEROUPPER

  (31) 0x402baf MOVSXD	%EAX,%RCX

  (31) 0x402bb2 VMOVSS	-0x38(%RBP),%XMM1

  (31) 0x402bb7 VMAXSS	(%R13,%RCX,4),%XMM1,%XMM7

  (31) 0x402bbe LEA	(,%RCX,4),%RDX

  (31) 0x402bc6 VMOVSS	%XMM7,-0x38(%RBP)

  (31) 0x402bcb CMP	%R12D,%EAX

  (31) 0x402bce JGE	402c40

  (31) 0x402bd0 VMAXSS	0x4(%R13,%RDX,1),%XMM7,%XMM7

  (31) 0x402bd7 LEA	0x2(%RAX),%ECX

  (31) 0x402bda VMOVSS	%XMM7,-0x38(%RBP)

  (31) 0x402bdf CMP	%R12D,%ECX

  (31) 0x402be2 JG	402c40

  (31) 0x402be4 VMAXSS	0x8(%R13,%RDX,1),%XMM7,%XMM1

  (31) 0x402beb LEA	0x3(%RAX),%ECX

  (31) 0x402bee VMOVSS	%XMM1,-0x38(%RBP)

  (31) 0x402bf3 CMP	%R12D,%ECX

  (31) 0x402bf6 JG	402c40

  (31) 0x402bf8 VMAXSS	0xc(%R13,%RDX,1),%XMM1,%XMM1

  (31) 0x402bff LEA	0x4(%RAX),%ECX

  (31) 0x402c02 VMOVSS	%XMM1,-0x38(%RBP)

  (31) 0x402c07 CMP	%R12D,%ECX

  (31) 0x402c0a JG	402c40

  (31) 0x402c0c VMAXSS	0x10(%R13,%RDX,1),%XMM1,%XMM7

  (31) 0x402c13 LEA	0x5(%RAX),%ECX

  (31) 0x402c16 VMOVSS	%XMM7,-0x38(%RBP)

  (31) 0x402c1b CMP	%R12D,%ECX

  (31) 0x402c1e JG	402c40

  (31) 0x402c20 VMAXSS	0x14(%R13,%RDX,1),%XMM7,%XMM7

  (31) 0x402c27 ADD	$0x6,%EAX

  (31) 0x402c2a VMOVSS	%XMM7,-0x38(%RBP)

  (31) 0x402c2f CMP	%R12D,%EAX

  (31) 0x402c32 JG	402c40

  (31) 0x402c34 VMAXSS	0x18(%R13,%RDX,1),%XMM7,%XMM1

  (31) 0x402c3b VMOVSS	%XMM1,-0x38(%RBP)

    (30) 0x402c40 MOVL	$0,-0x34(%RBP)

    (30) 0x402c47 MOV	%R13,%R14

    (30) 0x402c4a NOPW	(%RAX,%RAX,1)

      (27) 0x402c50 VMOVSS	(%R14),%XMM0

      (27) 0x402c55 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (27) 0x402c5a ADD	$0x4,%R14

      (27) 0x402c5e CALL	401110 <expf@plt>

      (27) 0x402c63 VADDSS	-0x34(%RBP),%XMM0,%XMM3

      (27) 0x402c68 VMOVSS	%XMM3,-0x34(%RBP)

      (27) 0x402c6d CMP	%R14,%RBX

      (27) 0x402c70 JNE	402c50

    (30) 0x402c72 MOV	-0x40(%RBP),%R14

    (30) 0x402c76 MOV	%R13,%R15

    (30) 0x402c79 NOPL	(%RAX)

      (28) 0x402c80 VMOVSS	(%R15),%XMM0

      (28) 0x402c85 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (28) 0x402c8a ADD	$0x4,%R15

      (28) 0x402c8e ADD	$0x4,%R14

      (28) 0x402c92 CALL	401110 <expf@plt>

      (28) 0x402c97 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (28) 0x402c9c VMOVSS	%XMM0,-0x4(%R14)

      (28) 0x402ca2 CMP	%R15,%RBX

      (28) 0x402ca5 JNE	402c80

    (30) 0x402ca7 CMP	-0x58(%RBP),%R12

    (30) 0x402cab JE	402d30

    (30) 0x402cb1 MOV	-0x68(%RBP),%RAX

    (30) 0x402cb5 MOV	-0x50(%RBP),%R15

    (30) 0x402cb9 XOR	%ESI,%ESI

    (30) 0x402cbb MOV	-0x70(%RBP),%R14

    (30) 0x402cbf ADD	%RAX,-0x40(%RBP)

    (30) 0x402cc3 ADD	%RAX,%R13

    (30) 0x402cc6 MOV	-0x48(%RBP),%EAX

    (30) 0x402cc9 MOV	%R15,%RDI

    (30) 0x402ccc ADD	%R14,%RBX

    (30) 0x402ccf SUB	-0x44(%RBP),%EAX

    (30) 0x402cd2 LEA	0x4(,%RAX,4),%RDX

    (30) 0x402cda CALL	401040 <memset@plt>

    (30) 0x402cdf VMOVSS	-0x34(%RBP),%XMM7

    (30) 0x402ce4 MOV	-0x60(%RBP),%RAX

    (30) 0x402ce8 VMOVSS	%XMM7,(%RAX,%R12,4)

    (30) 0x402cee INC	%R12

    (30) 0x402cf1 LEA	(%R15,%R14,1),%RAX

    (30) 0x402cf5 MOV	%RAX,-0x50(%RBP)

    (30) 0x402cf9 MOV	%R12D,-0x44(%RBP)

    (30) 0x402cfd CMP	$0x6,%R12

    (30) 0x402d01 JA	402b50

(32) 0x402d07 VMOVSS	0x14f5(%RIP),%XMM3

(32) 0x402d0f XOR	%EAX,%EAX

(32) 0x402d11 VMOVSS	%XMM3,-0x38(%RBP)

(32) 0x402d16 JMP	402baf

0x402d1b NOPL	(%RAX,%RAX,1)

    (30) 0x402d20 VZEROUPPER

    (30) 0x402d23 JMP	402c40

0x402d28 NOPL	(%RAX,%RAX,1)

0x402d30 VMOVSS	-0x34(%RBP),%XMM2

0x402d35 MOV	-0x60(%RBP),%RAX

0x402d39 VMOVSS	%XMM2,(%RAX,%R12,4)

0x402d3f ADD	$0x40,%RSP

0x402d43 POP	%RBX

0x402d44 POP	%R10

0x402d46 POP	%R12

0x402d48 POP	%R13

0x402d4a POP	%R14

0x402d4c POP	%R15

0x402d4e POP	%RBP

0x402d4f LEA	-0x8(%R10),%RSP

0x402d53 RET

0x402d54 RET

0x402d55 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-znver5-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-znver5-256

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.63 to 1.17 cycles (5.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.63 to 0.47 cycles (14.10x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	52
nb uops	53
loop length	189
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.63
Dispatch	3.00
Overall L1	6.63

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.63 cycles. At this rate:

1% of peak load performance is reached (3.02 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.63 to 3.00 cycles (2.21x speedup).

ASM code

In the binary file, the address of the function is: 402ad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402d54 <_Z7softmaxPKfPfS1_i+0x284>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ECX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(,%RAX,4),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R12D,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDI),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RCX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA -0x2(%RCX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP $0x6,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 402d07 <_Z7softmaxPKfPfS1_i+0x237>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSS %XMM2,(%RAX,%R12,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (6.3%)
ADD $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x8(%R10),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-znver5-256

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.63 to 1.17 cycles (5.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	52
nb uops	53
loop length	189
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.63
Dispatch	3.00
Overall L1	6.63

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.63 cycles. At this rate:

1% of peak load performance is reached (3.02 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.06 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 402ad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 402d54 <_Z7softmaxPKfPfS1_i+0x284>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
LEA 0x8(%RSP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %ECX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSHQ -0x8(%R10)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	N/A
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(,%RAX,4),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R12D,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA 0x4(%RDI),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SAL $0x2,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA -0x1(%RCX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
LEA -0x2(%RCX),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP $0x6,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 402d07 <_Z7softmaxPKfPfS1_i+0x237>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0.33-0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSS %XMM2,(%RAX,%R12,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (6.3%)
ADD $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x8(%R10),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	5.78	0.38
▼Loop 32 - attention_v2.cpp:43-61 - attention-gcc-znver5-256–	0.00	0.00
▼Loop 31 - attention_v2.cpp:43-61 - attention-gcc-znver5-256–	0.08	0.00
▼Loop 30 - attention_v2.cpp:43-61 - attention-gcc-znver5-256–	0.23	0.01
○Loop 28 - attention_v2.cpp:55-56 - attention-gcc-znver5-256	3.23	0.22
○Loop 27 - attention_v2.cpp:52-53 - attention-gcc-znver5-256	2.03	0.13
○Loop 29 - attention_v2.cpp:47-48 - attention-gcc-znver5-256	0.23	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code