| Loop Id: 76 | Module: attention-avx512 | Source: attention.cpp:27-33 | Coverage: 0.84% |
|---|
| Loop Id: 76 | Module: attention-avx512 | Source: attention.cpp:27-33 | Coverage: 0.84% |
|---|
0x3b10 VCVTSD2SS %XMM0,%XMM0,%XMM0 |
0x3b14 MOV 0x30(%RSP),%RCX |
0x3b19 ADD %EAX,%ECX |
0x3b1b MOV 0x58(%RSP),%R9 |
0x3b20 VMOVSS %XMM0,(%R9,%RCX,4) |
0x3b26 INC %RAX |
0x3b29 MOV 0x28(%RSP),%R13 |
0x3b2e CMP %R13,%RAX |
0x3b31 MOV 0x50(%RSP),%R15 |
0x3b36 JE 3af0 |
0x3b38 CMPL $0x3,0x80(%RSP) |
0x3b40 JAE 3b60 |
0x3b42 VXORPS %XMM0,%XMM0,%XMM0 |
0x3b46 XOR %R13D,%R13D |
0x3b49 MOV 0x48(%RSP),%R9 |
0x3b4e JMP 3c12 |
0x3b60 VXORPS %XMM0,%XMM0,%XMM0 |
0x3b64 MOV %RAX,%R11 |
0x3b67 XOR %R13D,%R13D |
0x3b6a MOV 0x48(%RSP),%R9 |
0x3b6f NOP |
(73) 0x3b70 LEA (%R10,%R13,1),%R15D |
(73) 0x3b74 VMOVSS (%R14,%R15,4),%XMM1 |
(73) 0x3b7a VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(73) 0x3b7e MOV %R11D,%R15D |
(73) 0x3b81 VMOVSS (%R9,%R15,4),%XMM2 |
(73) 0x3b87 VCVTSS2SD %XMM2,%XMM2,%XMM2 |
(73) 0x3b8b LEA 0x1(%R10,%R13,1),%R15D |
(73) 0x3b90 VMOVSS (%R14,%R15,4),%XMM3 |
(73) 0x3b96 VCVTSS2SD %XMM3,%XMM3,%XMM3 |
(73) 0x3b9a LEA (%R12,%R11,1),%R15D |
(73) 0x3b9e VMOVSS (%R9,%R15,4),%XMM4 |
(73) 0x3ba4 VCVTSS2SD %XMM4,%XMM4,%XMM4 |
(73) 0x3ba8 LEA 0x2(%R10,%R13,1),%R15D |
(73) 0x3bad VMOVSS (%R14,%R15,4),%XMM5 |
(73) 0x3bb3 VFMADD213SD %XMM0,%XMM1,%XMM2 |
(73) 0x3bb8 VCVTSS2SD %XMM5,%XMM5,%XMM0 |
(73) 0x3bbc LEA (%R8,%R11,1),%R15D |
(73) 0x3bc0 VMOVSS (%R9,%R15,4),%XMM1 |
(73) 0x3bc6 VFMADD213SD %XMM2,%XMM3,%XMM4 |
(73) 0x3bcb VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(73) 0x3bcf LEA 0x3(%R10,%R13,1),%R15D |
(73) 0x3bd4 VMOVSS (%R14,%R15,4),%XMM2 |
(73) 0x3bda VFMADD213SD %XMM4,%XMM0,%XMM1 |
(73) 0x3bdf VCVTSS2SD %XMM2,%XMM2,%XMM2 |
(73) 0x3be3 LEA (%RSI,%R11,1),%R15D |
(73) 0x3be7 VMOVSS (%R9,%R15,4),%XMM0 |
(73) 0x3bed VCVTSS2SD %XMM0,%XMM0,%XMM0 |
(73) 0x3bf1 VFMADD213SD %XMM1,%XMM2,%XMM0 |
(73) 0x3bf6 ADD $0x4,%R13 |
(73) 0x3bfa ADD %RDI,%R11 |
(73) 0x3bfd CMP %R13,%RDX |
(73) 0x3c00 JNE 3b70 |
0x3c06 CMPQ $0,0x10(%RSP) |
0x3c0c JE 3b10 |
0x3c12 MOV %R12,%R11 |
0x3c15 IMUL %R13,%R11 |
0x3c19 ADD %RAX,%R11 |
0x3c1c ADD %R10D,%R13D |
0x3c1f MOV 0x10(%RSP),%R15 |
0x3c24 NOPW %CS:(%RAX,%RAX,1) |
(77) 0x3c30 MOV %R13D,%ECX |
(77) 0x3c33 VMOVSS (%R14,%RCX,4),%XMM1 |
(77) 0x3c39 VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(77) 0x3c3d MOV %R11D,%ECX |
(77) 0x3c40 VMOVSS (%R9,%RCX,4),%XMM2 |
(77) 0x3c46 VCVTSS2SD %XMM2,%XMM2,%XMM2 |
(77) 0x3c4a VFMADD231SD %XMM2,%XMM1,%XMM0 |
(77) 0x3c4f ADD %R12,%R11 |
(77) 0x3c52 INC %R13D |
(77) 0x3c55 DEC %R15 |
(77) 0x3c58 JNE 3c30 |
0x3c5a JMP 3b10 |
/home/eoseret/Applications/llm-attention/attention.cpp: 27 - 33 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-avx512 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.84 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.65 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.61 |
| Bottlenecks | |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-30,attention.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.92 |
| CQA cycles if no scalar integer | 2.08 |
| CQA cycles if FP arith vectorized | 5.92 |
| CQA cycles if fully vectorized | 0.47 |
| Front-end cycles | 5.92 |
| P0 cycles | 3.08 |
| P1 cycles | 3.08 |
| P2 cycles | 3.67 |
| P3 cycles | 3.67 |
| P4 cycles | 1.00 |
| P5 cycles | 3.08 |
| P6 cycles | 3.08 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 22.67 |
| Nb uops | 23.67 |
| Nb loads | 7.33 |
| Nb stores | 1.00 |
| Nb stack references | 7.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 54.67 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.67 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 9.44 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 16.98 |
| Vector-efficiency ratio all | 12.29 |
| Vector-efficiency ratio load | 10.59 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 13.21 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.69 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.71 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-30,attention.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 6.00 |
| CQA cycles if fully vectorized | 0.47 |
| Front-end cycles | 6.00 |
| P0 cycles | 3.25 |
| P1 cycles | 3.25 |
| P2 cycles | 3.50 |
| P3 cycles | 3.50 |
| P4 cycles | 1.00 |
| P5 cycles | 3.25 |
| P6 cycles | 3.25 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 23.00 |
| Nb uops | 24.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 7.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 52.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 10.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 20.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 10.42 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 13.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.61 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.69 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-30,attention.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 2.25 |
| CQA cycles if FP arith vectorized | 6.75 |
| CQA cycles if fully vectorized | 0.54 |
| Front-end cycles | 6.75 |
| P0 cycles | 3.50 |
| P1 cycles | 3.50 |
| P2 cycles | 4.00 |
| P3 cycles | 4.00 |
| P4 cycles | 1.00 |
| P5 cycles | 3.50 |
| P6 cycles | 3.50 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 26.00 |
| Nb uops | 27.00 |
| Nb loads | 8.00 |
| Nb stores | 1.00 |
| Nb stack references | 7.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.48 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 60.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 3.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 8.33 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 14.29 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 10.94 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 13.39 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.50 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.67 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.43 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention.cpp:27-27,attention.cpp:30-30,attention.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 5.00 |
| CQA cycles if fully vectorized | 0.39 |
| Front-end cycles | 5.00 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 3.50 |
| P3 cycles | 3.50 |
| P4 cycles | 1.00 |
| P5 cycles | 2.50 |
| P6 cycles | 2.50 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 19.00 |
| Nb uops | 20.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 7.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 52.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 10.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 16.67 |
| Vector-efficiency ratio all | 11.88 |
| Vector-efficiency ratio load | 10.42 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 22.67 |
| nb uops | 23.67 |
| loop length | 97.67 |
| used x86 registers | 8.33 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 5.92 cycles |
| front end | 5.92 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.08 | 3.08 | 3.67 | 3.67 | 1.00 | 3.08 | 3.08 | 1.00 |
| cycles | 3.08 | 3.08 | 3.67 | 3.67 | 1.00 | 3.08 | 3.08 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 5.92 |
| Dispatch | 3.67 |
| Data deps. | 0.00 |
| Overall L1 | 5.92 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 9% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 11% |
| load | 10% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 12% |
| load | 10% |
| store | 6% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 13% |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 23 |
| nb uops | 24 |
| loop length | 102 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 6.00 cycles |
| front end | 6.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.25 | 3.25 | 3.50 | 3.50 | 1.00 | 3.25 | 3.25 | 1.00 |
| cycles | 3.25 | 3.25 | 3.50 | 3.50 | 1.00 | 3.25 | 3.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 6.00 |
| Dispatch | 3.50 |
| Data deps. | 0.00 |
| Overall L1 | 6.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 11% |
| load | 10% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 12% |
| load | 10% |
| store | 6% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 13% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| MOV 0x30(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADD %EAX,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x58(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM0,(%R9,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x28(%RSP),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| CMP %R13,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV 0x50(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| JE 3af0 <main+0x1500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMPL $0x3,0x80(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (6.3%) |
| JAE 3b60 <main+0x1570> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV 0x48(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| JMP 3c12 <main+0x1622> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| MOV %R12,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| IMUL %R13,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| ADD %RAX,%R11 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD %R10D,%R13D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x10(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| JMP 3b10 <main+0x1520> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 26 |
| nb uops | 27 |
| loop length | 113 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 6.75 cycles |
| front end | 6.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 3.50 | 4.00 | 4.00 | 1.00 | 3.50 | 3.50 | 1.00 |
| cycles | 3.50 | 3.50 | 4.00 | 4.00 | 1.00 | 3.50 | 3.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 6.75 |
| Dispatch | 4.00 |
| Data deps. | 0.00 |
| Overall L1 | 6.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 8% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 11% |
| load | 10% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 11% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 12% |
| load | 10% |
| store | 6% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 13% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| MOV 0x30(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADD %EAX,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x58(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM0,(%R9,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x28(%RSP),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| CMP %R13,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV 0x50(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| JE 3af0 <main+0x1500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMPL $0x3,0x80(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (6.3%) |
| JAE 3b60 <main+0x1570> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV 0x48(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| CMPQ $0,0x10(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| JE 3b10 <main+0x1520> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOV %R12,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| IMUL %R13,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| ADD %RAX,%R11 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| ADD %R10D,%R13D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x10(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| JMP 3b10 <main+0x1520> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| Function | main |
| Source file and lines | attention.cpp:27-33 |
| Module | attention-avx512 |
| nb instructions | 19 |
| nb uops | 20 |
| loop length | 78 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 5.00 cycles |
| front end | 5.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 3.50 | 3.50 | 1.00 | 2.50 | 2.50 | 1.00 |
| cycles | 2.50 | 2.50 | 3.50 | 3.50 | 1.00 | 2.50 | 2.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 5.00 |
| Dispatch | 3.50 |
| Data deps. | 0.00 |
| Overall L1 | 5.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 10% |
| load | 10% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 11% |
| load | 10% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| MOV 0x30(%RSP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADD %EAX,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x58(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM0,(%R9,%RCX,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV 0x28(%RSP),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| CMP %R13,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV 0x50(%RSP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| JE 3af0 <main+0x1500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMPL $0x3,0x80(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (6.3%) |
| JAE 3b60 <main+0x1570> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| XOR %R13D,%R13D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| MOV 0x48(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| CMPQ $0,0x10(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | N/A |
| JE 3b10 <main+0x1520> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
