OV - attention-avx512 - Loop 65

0x3fb0 ADD	$0x2,%R9

0x3fb4 CMP	%RCX,%R9

0x3fb7 JE	4010

0x3fb9 CMP	$0x7,%EAX

0x3fbc JB	3fdb

0x3fbe MOV	%RSI,%R10

0x3fc1 NOPW	%CS:(%RAX,%RAX,1)

  (67) 0x3fd0 ADD	$-0x8,%R10

  (67) 0x3fd4 JNE	3fd0

0x3fd6 TEST	%RDX,%RDX

0x3fd9 JE	3fe5

0x3fdb MOV	%RDX,%R10

0x3fde XCHG	%AX,%AX

  (63) 0x3fe0 DEC	%R10

  (63) 0x3fe3 JNE	3fe0

0x3fe5 CMP	$0x7,%EAX

0x3fe8 JB	3ffc

0x3fea MOV	%RSI,%R10

0x3fed NOPL	(%RAX)

  (66) 0x3ff0 ADD	$-0x8,%R10

  (66) 0x3ff4 JNE	3ff0

0x3ff6 TEST	$0x7,%R12B

0x3ffa JE	3fb0

0x3ffc MOV	%RDX,%R10

0x3fff NOP

  (64) 0x4000 DEC	%R10

  (64) 0x4003 JNE	4000

0x4005 JMP	3fb0

/home/eoseret/Applications/llm-attention/attention.cpp: 27 - 30

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.36
Front-end cycles	5.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.11
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.36
Front-end cycles	5.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.11
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-30
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27-30.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27,30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.36 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	20
nb uops	20
loop length	65
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	0.00	0.00	0.00	3.00	3.00	0.00
cycles	3.00	3.00	0.00	0.00	0.00	3.00	3.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Dispatch	3.00
Overall L1	5.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.00 cycles (1.67x speedup).

ASM code

In the binary file, the address of the loop is: 3fb9

Instruction	Nb FU	P0	P1	P5	P6	Latency	Recip. throughput	Vectorization
ADD $0x2,%R9	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4010 <main+0x1a20>	1	0.50	0	0	0.50	0	0.50-1	N/A
CMP $0x7,%EAX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JB 3fdb <main+0x19eb>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0.25	N/A
TEST %RDX,%RDX	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 3fe5 <main+0x19f5>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0.25	N/A
CMP $0x7,%EAX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JB 3ffc <main+0x1a0c>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0.25	N/A
TEST $0x7,%R12B	1	0.25	0.25	0.25	0.25	1	0.25	N/A
JE 3fb0 <main+0x19c0>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOP	1	0	0	0	0	0	0.25	N/A
JMP 3fb0 <main+0x19c0>	1	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention.cpp:27-30
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27-30.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27,30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.36 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	20
nb uops	20
loop length	65
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	0.00	0.00	0.00	3.00	3.00	0.00
cycles	3.00	3.00	0.00	0.00	0.00	3.00	3.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.00
Dispatch	3.00
Overall L1	5.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.00 cycles (1.67x speedup).

ASM code

In the binary file, the address of the loop is: 3fb9

Instruction	Nb FU	P0	P1	P5	P6	Latency	Recip. throughput	Vectorization
ADD $0x2,%R9	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
CMP %RCX,%R9	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 4010 <main+0x1a20>	1	0.50	0	0	0.50	0	0.50-1	N/A
CMP $0x7,%EAX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JB 3fdb <main+0x19eb>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0.25	N/A
TEST %RDX,%RDX	1	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 3fe5 <main+0x19f5>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0.25	N/A
CMP $0x7,%EAX	1	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JB 3ffc <main+0x1a0c>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0.25	N/A
TEST $0x7,%R12B	1	0.25	0.25	0.25	0.25	1	0.25	N/A
JE 3fb0 <main+0x19c0>	1	0.50	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0.25	scal (12.5%)
NOP	1	0	0	0	0	0	0.25	N/A
JMP 3fb0 <main+0x19c0>	1	0	0	0	1	0	1-2	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code