OV - attention-avx512 - Loop 56

	Loop Id: 56	Module: attention-avx512	Source: attention.cpp:239-241	Coverage: 0.03%

0x4170 INC	%R10

0x4173 ADD	0x10(%RSP),%R9

0x4178 ADD	$0x4,%R8

0x417c CMP	%RAX,%R10

0x417f MOV	0x48(%RSP),%R13

0x4184 MOV	0x50(%RSP),%R15

0x4189 JE	4140

0x418b MOV	0x28(%RSP),%R13

0x4190 CMP	$0x4,%R13D

0x4194 JAE	41b0

0x4196 XOR	%R15D,%R15D

0x4199 MOV	0x20(%RSP),%RDI

0x419e LEA	(,%RDI,4),%RDI

0x41a6 MOV	%R13,%RSI

0x41a9 JMP	4291

0x41b0 LEA	(%RBX,%R10,4),%R11

0x41b4 CMP	$0x10,%R13D

0x41b8 JAE	41c0

0x41ba XOR	%R13D,%R13D

0x41bd JMP	4239

0x41c0 XOR	%R15D,%R15D

0x41c3 VMOVDQA64	%ZMM4,%ZMM6

0x41c9 VMOVDQA64	%ZMM3,%ZMM7

0x41cf NOP

  (54) 0x41d0 VPMULLQ	%ZMM0,%ZMM6,%ZMM8

  (54) 0x41d6 VMOVUPS	(%R9,%R15,4),%YMM9

  (54) 0x41dc VMOVUPS	0x20(%R9,%R15,4),%YMM10

  (54) 0x41e3 KXNORB	%K0,%K0,%K1

  (54) 0x41e7 VSCATTERQPS	%YMM9,(%R11,%ZMM8,4){%K1}

  (54) 0x41ee VPMULLQ	%ZMM0,%ZMM7,%ZMM8

  (54) 0x41f4 KXNORB	%K0,%K0,%K1

  (54) 0x41f8 VSCATTERQPS	%YMM10,(%R11,%ZMM8,4){%K1}

  (54) 0x41ff ADD	$0x10,%R15

  (54) 0x4203 VPADDQ	%ZMM5,%ZMM6,%ZMM6

  (54) 0x4209 VPADDQ	%ZMM5,%ZMM7,%ZMM7

  (54) 0x420f CMP	%R15,%RCX

  (54) 0x4212 JNE	41d0

0x4214 CMP	%ECX,%R13D

0x4217 MOV	0x20(%RSP),%RDI

0x421c LEA	(,%RDI,4),%RDI

0x4224 JE	4170

0x422a MOV	%R13,%RSI

0x422d MOV	%RCX,%R13

0x4230 MOV	%RCX,%R15

0x4233 TEST	$0xc,%R12B

0x4237 JE	4291

0x4239 VPBROADCASTQ	%R13,%YMM6

0x423f VPOR	%YMM1,%YMM6,%YMM6

0x4243 NOPW	%CS:(%RAX,%RAX,1)

  (58) 0x4250 VMOVUPS	(%R9,%R13,4),%XMM7

  (58) 0x4256 VPMULLQ	%YMM0,%YMM6,%YMM8

  (58) 0x425c KXNORW	%K0,%K0,%K1

  (58) 0x4260 VSCATTERQPS	%XMM7,(%R11,%YMM8,4){%K1}

  (58) 0x4267 ADD	$0x4,%R13

  (58) 0x426b VPADDQ	%YMM2,%YMM6,%YMM6

  (58) 0x426f CMP	%R13,%RDX

  (58) 0x4272 JNE	4250

0x4274 MOV	%RDX,%R15

0x4277 MOV	0x28(%RSP),%RSI

0x427c CMP	%EDX,%ESI

0x427e MOV	0x20(%RSP),%RDI

0x4283 LEA	(,%RDI,4),%RDI

0x428b JE	4170

0x4291 MOV	%RDI,%R11

0x4294 IMUL	%R15,%R11

0x4298 ADD	%R8,%R11

0x429b NOPL	(%RAX,%RAX,1)

  (57) 0x42a0 VMOVD	(%R9,%R15,4),%XMM6

  (57) 0x42a6 VMOVD	%XMM6,(%R11)

  (57) 0x42ab INC	%R15

  (57) 0x42ae ADD	%RDI,%R11

  (57) 0x42b1 CMP	%R15,%RSI

  (57) 0x42b4 JNE	42a0

0x42b6 JMP	4170

/home/eoseret/Applications/llm-attention/attention.cpp: 239 - 241

--------------------------------------------------------------------------------

239:       for (int i = 0; i < context_size; ++i)

240:          for (int j = 0; j < dim; ++j)// vectorized

241:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:239-240
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	3.75
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	0.95
Front-end cycles	11.75
P0 cycles	6.50
P1 cycles	6.42
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.58
P6 cycles	6.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.45
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	13.64
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	17.65
Vector-efficiency ratio all	20.17
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.43

Metric	Value
CQA speedup if no scalar integer	3.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:239-240
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	3.75
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	0.95
Front-end cycles	11.75
P0 cycles	6.50
P1 cycles	6.42
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.58
P6 cycles	6.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.45
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	13.64
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	17.65
Vector-efficiency ratio all	20.17
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.43

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:239-241
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:239-241.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:239-240.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 3.75 cycles (3.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.75 to 0.95 cycles (12.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	47
nb uops	47
loop length	202
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	4
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.42	4.00	4.00	0.00	6.58	6.50	0.00
cycles	6.50	6.42	4.00	4.00	0.00	6.58	6.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	6.58
Overall L1	11.75

Vectorization ratios

all	13%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

all	20%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

4% of peak load performance is reached (5.45 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.75 to 6.58 cycles (1.78x speedup).

ASM code

In the binary file, the address of the loop is: 418b

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD 0x10(%RSP),%R9	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP %RAX,%R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV 0x48(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0x50(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4140 <main+0x1b50>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x28(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP $0x4,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 41b0 <main+0x1bc0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 4291 <main+0x1ca1>	1	0	0	0	0	0	1	0	1-2	N/A
LEA (%RBX,%R10,4),%R11	1	0	0.50	0	0	0.50	0	1	0.50	N/A
CMP $0x10,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 41c0 <main+0x1bd0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4239 <main+0x1c49>	1	0	0	0	0	0	1	0	1-2	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA64 %ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA64 %ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0.25	vect (100.0%)
NOP	1	0	0	0	0	0	0	0	0.25	N/A
CMP %ECX,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
JE 4170 <main+0x1b80>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 4291 <main+0x1ca1>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VPBROADCASTQ %R13,%YMM6	1	0	0	0	0	1	0	1	1	scal (12.5%)
VPOR %YMM1,%YMM6,%YMM6	1	0.33	0.33	0	0	0.33	0	1	0.33	vect (50.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x28(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %EDX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
JE 4170 <main+0x1b80>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %R15,%R11	1	0	1	0	0	0	0	3	1	N/A
ADD %R8,%R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 4170 <main+0x1b80>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention.cpp:239-241
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:239-241.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:239-240.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 3.75 cycles (3.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	47
nb uops	47
loop length	202
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	4
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.42	4.00	4.00	0.00	6.58	6.50	0.00
cycles	6.50	6.42	4.00	4.00	0.00	6.58	6.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	6.58
Overall L1	11.75

Vectorization ratios

all	13%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Vector efficiency ratios

all	20%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

4% of peak load performance is reached (5.45 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 418b

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD 0x10(%RSP),%R9	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP %RAX,%R10	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV 0x48(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0x50(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4140 <main+0x1b50>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x28(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP $0x4,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 41b0 <main+0x1bc0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 4291 <main+0x1ca1>	1	0	0	0	0	0	1	0	1-2	N/A
LEA (%RBX,%R10,4),%R11	1	0	0.50	0	0	0.50	0	1	0.50	N/A
CMP $0x10,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 41c0 <main+0x1bd0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4239 <main+0x1c49>	1	0	0	0	0	0	1	0	1-2	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA64 %ZMM4,%ZMM6	1	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQA64 %ZMM3,%ZMM7	1	0	0	0	0	0	0	0	0.25	vect (100.0%)
NOP	1	0	0	0	0	0	0	0	0.25	N/A
CMP %ECX,%R13D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
JE 4170 <main+0x1b80>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R13,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 4291 <main+0x1ca1>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VPBROADCASTQ %R13,%YMM6	1	0	0	0	0	1	0	1	1	scal (12.5%)
VPOR %YMM1,%YMM6,%YMM6	1	0.33	0.33	0	0	0.33	0	1	0.33	vect (50.0%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x28(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %EDX,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x20(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	N/A
LEA (,%RDI,4),%RDI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
JE 4170 <main+0x1b80>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %R15,%R11	1	0	1	0	0	0	0	3	1	N/A
ADD %R8,%R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 4170 <main+0x1b80>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code