OV - attention-avx512 - Loop 54

	Loop Id: 54	Module: attention-avx512	Source: attention.cpp:240-241	Coverage: 0.19%

0x41d0 VPMULLQ	%ZMM0,%ZMM6,%ZMM8

0x41d6 VMOVUPS	(%R9,%R15,4),%YMM9    [1]

0x41dc VMOVUPS	0x20(%R9,%R15,4),%YMM10    [1]

0x41e3 KXNORB	%K0,%K0,%K1

0x41e7 VSCATTERQPS	%YMM9,(%R11,%ZMM8,4){%K1}    [2]

0x41ee VPMULLQ	%ZMM0,%ZMM7,%ZMM8

0x41f4 KXNORB	%K0,%K0,%K1

0x41f8 VSCATTERQPS	%YMM10,(%R11,%ZMM8,4){%K1}    [2]

0x41ff ADD	$0x10,%R15

0x4203 VPADDQ	%ZMM5,%ZMM6,%ZMM6

0x4209 VPADDQ	%ZMM5,%ZMM7,%ZMM7

0x420f CMP	%R15,%RCX

0x4212 JNE	41d0

/home/eoseret/Applications/llm-attention/attention.cpp: 240 - 241

--------------------------------------------------------------------------------

240:          for (int j = 0; j < dim; ++j)// vectorized

241:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:240-241
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	17.00
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	14.38
Front-end cycles	17.00
P0 cycles	6.00
P1 cycles	1.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	16.00
P5 cycles	6.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	68.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	75.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.18
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:240-241
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	17.00
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	17.00
CQA cycles if fully vectorized	14.38
Front-end cycles	17.00
P0 cycles	6.00
P1 cycles	1.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	16.00
P5 cycles	6.00
P6 cycles	1.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	68.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	75.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:240-241
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:240-241.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using 75% register length (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 17.00 to 14.38 cycles (1.18x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241
VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	13
nb uops	68
loop length	68
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	1.00	9.00	9.00	16.00	6.00	1.00	0.00
cycles	6.00	1.00	9.00	9.00	16.00	6.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Dispatch	16.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	50%
store	50%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

2% of peak load performance is reached (3.76 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.53 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.00 to 16.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the loop is: 41d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	Latency	Recip. throughput	Vectorization
VPMULLQ %ZMM0,%ZMM6,%ZMM8	3	1.50	0	0	0	0	1.50	0	15	1.50	vect (100.0%)
VMOVUPS (%R9,%R15,4),%YMM9	1	0	0	0.50	0.50	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x20(%R9,%R15,4),%YMM10	1	0	0	0.50	0.50	0	0	0	5-6	0.50	vect (50.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM9,(%R11,%ZMM8,4){%K1}	27	0	0	4	4	8	1	0	15	11	vect (50.0%)
VPMULLQ %ZMM0,%ZMM7,%ZMM8	3	1.50	0	0	0	0	1.50	0	15	1.50	vect (100.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM10,(%R11,%ZMM8,4){%K1}	27	0	0	4	4	8	1	0	15	11	vect (50.0%)
ADD $0x10,%R15	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
VPADDQ %ZMM5,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	1	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	1	0.50	vect (100.0%)
CMP %R15,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
JNE 41d0 <main+0x1be0>	1	0.50	0	0	0	0	0	0.50	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:240-241
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:240-241.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241
VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:241
- /home/eoseret/Applications/llm-attention/attention.cpp:241

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	13
nb uops	68
loop length	68
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	5
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	1.00	9.00	9.00	16.00	6.00	1.00	0.00
cycles	6.00	1.00	9.00	9.00	16.00	6.00	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.00
Dispatch	16.00
Data deps.	1.00
Overall L1	17.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	50%
store	50%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.00 cycles. At this rate:

2% of peak load performance is reached (3.76 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.53 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 41d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	Latency	Recip. throughput	Vectorization
VPMULLQ %ZMM0,%ZMM6,%ZMM8	3	1.50	0	0	0	0	1.50	0	15	1.50	vect (100.0%)
VMOVUPS (%R9,%R15,4),%YMM9	1	0	0	0.50	0.50	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x20(%R9,%R15,4),%YMM10	1	0	0	0.50	0.50	0	0	0	5-6	0.50	vect (50.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM9,(%R11,%ZMM8,4){%K1}	27	0	0	4	4	8	1	0	15	11	vect (50.0%)
VPMULLQ %ZMM0,%ZMM7,%ZMM8	3	1.50	0	0	0	0	1.50	0	15	1.50	vect (100.0%)
KXNORB %K0,%K0,%K1	1	1	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM10,(%R11,%ZMM8,4){%K1}	27	0	0	4	4	8	1	0	15	11	vect (50.0%)
ADD $0x10,%R15	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
VPADDQ %ZMM5,%ZMM6,%ZMM6	1	0.50	0	0	0	0	0.50	0	1	0.50	vect (100.0%)
VPADDQ %ZMM5,%ZMM7,%ZMM7	1	0.50	0	0	0	0	0.50	0	1	0.50	vect (100.0%)
CMP %R15,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	1	0.25	N/A
JNE 41d0 <main+0x1be0>	1	0.50	0	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code