OV - attention-avx512 - Loop 43

0x4dd0 VMOVSS	(%RDI,%R15,4),%XMM0    [2]

0x4dd6 VSUBSS	%XMM1,%XMM0,%XMM0

0x4dda VZEROUPPER

0x4ddd CALL	1130 <expf@plt>

0x4de2 VMOVAPS	0x30(%RSP),%XMM1    [1]

0x4de8 MOV	0x10(%RSP),%RDI    [1]

0x4ded VMULSS	0x40(%RSP),%XMM0,%XMM0    [1]

0x4df3 VMOVSS	%XMM0,(%RBX,%R15,4)    [3]

0x4df9 INC	%R15

0x4dfc CMP	%R15,%R13

0x4dff JNE	4dd0

/home/eoseret/Applications/llm-attention/attention.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	2.24
CQA speedup if fully vectorized	10.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	3.50
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.56
CQA cycles if fully vectorized	0.34
Front-end cycles	3.50
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	14.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.57
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.29
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	4.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	2.24
CQA speedup if fully vectorized	10.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	3.50
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	1.56
CQA cycles if fully vectorized	0.34
Front-end cycles	3.50
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	14.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.57
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.29
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	4.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	33.33
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is peel/tail loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 2.75 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.08x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction
1: multiply

The binary loop is loading 32 bytes (8 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	11
nb uops	14
loop length	49
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	2.00	2.00	2.00	1.00	1.50	2.00
cycles	1.50	1.00	2.00	2.00	2.00	1.00	1.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	2.00
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

FP

all	20%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

FP

all	10%
load	12%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

7% of peak load performance is reached (9.14 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the loop is: 4dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVSS (%RDI,%R15,4),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VSUBSS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1130 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x30(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV 0x10(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMULSS 0x40(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,(%RBX,%R15,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4dd0 <main+0x27e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is peel/tail loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 2.75 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.08x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: addition or subtraction
1: multiply

The binary loop is loading 32 bytes (8 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	11
nb uops	14
loop length	49
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	2.00	2.00	2.00	1.00	1.50	2.00
cycles	1.50	1.00	2.00	2.00	2.00	1.00	1.50	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	2.00
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

FP

all	20%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	33%
load	33%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

FP

all	10%
load	12%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

7% of peak load performance is reached (9.14 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.14 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.00 cycles (1.75x speedup).

ASM code

In the binary file, the address of the loop is: 4dd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVSS (%RDI,%R15,4),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VSUBSS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1130 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x30(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
MOV 0x10(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMULSS 0x40(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMOVSS %XMM0,(%RBX,%R15,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,%R13	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4dd0 <main+0x27e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code