OV - attention-avx512 - Loop 38

	Loop Id: 38	Module: attention-avx512	Source: attention.cpp:52-53	Coverage: 0.13%

0x4ad0 VMOVDQA	%YMM4,0x200(%RSP)    [2]

0x4ad9 VMOVAPS	%YMM3,0x120(%RSP)    [2]

0x4ae2 VMOVAPS	%YMM2,0xe0(%RSP)    [2]

0x4aeb VMOVAPS	%YMM1,0x80(%RSP)    [2]

0x4af4 VMOVUPS	(%RDI,%R15,4),%YMM0    [1]

0x4afa VMOVUPS	0x20(%RDI,%R15,4),%YMM1    [1]

0x4b01 VMOVUPS	0x40(%RDI,%R15,4),%YMM2    [1]

0x4b08 VMOVUPS	0x60(%RDI,%R15,4),%YMM3    [1]

0x4b0f VMOVAPS	0x220(%RSP),%YMM4    [2]

0x4b18 VSUBPS	%YMM4,%YMM0,%YMM0

0x4b1c VSUBPS	%YMM4,%YMM1,%YMM1

0x4b20 VMOVAPS	%YMM1,0x1a0(%RSP)    [2]

0x4b29 VSUBPS	%YMM4,%YMM2,%YMM1

0x4b2d VMOVAPS	%YMM1,0x180(%RSP)    [2]

0x4b36 VSUBPS	%YMM4,%YMM3,%YMM1

0x4b3a VMOVAPS	%YMM1,0x1e0(%RSP)    [2]

0x4b43 CALL	10d0 <_ZGVdN8v_expf@plt>

0x4b48 VMOVAPS	%YMM0,0x1c0(%RSP)    [2]

0x4b51 VMOVAPS	0x1a0(%RSP),%YMM0    [2]

0x4b5a CALL	10d0 <_ZGVdN8v_expf@plt>

0x4b5f VMOVAPS	%YMM0,0x1a0(%RSP)    [2]

0x4b68 VMOVAPS	0x180(%RSP),%YMM0    [2]

0x4b71 CALL	10d0 <_ZGVdN8v_expf@plt>

0x4b76 VMOVAPS	%YMM0,0x180(%RSP)    [2]

0x4b7f VMOVAPS	0x1e0(%RSP),%YMM0    [2]

0x4b88 CALL	10d0 <_ZGVdN8v_expf@plt>

0x4b8d VMOVAPS	0x200(%RSP),%YMM4    [2]

0x4b96 VMOVAPS	0x120(%RSP),%YMM3    [2]

0x4b9f VMOVAPS	0xe0(%RSP),%YMM2    [2]

0x4ba8 VMOVAPS	0x80(%RSP),%YMM1    [2]

0x4bb1 MOV	0x10(%RSP),%RDI    [2]

0x4bb6 VADDPS	0x1c0(%RSP),%YMM1,%YMM1    [2]

0x4bbf VADDPS	0x1a0(%RSP),%YMM2,%YMM2    [2]

0x4bc8 VADDPS	0x180(%RSP),%YMM3,%YMM3    [2]

0x4bd1 VADDPS	%YMM4,%YMM0,%YMM4

0x4bd5 ADD	$0x20,%R15

0x4bd9 CMP	%R15,0x178(%RSP)    [2]

0x4be1 JNE	4ad0

/home/eoseret/Applications/llm-attention/attention.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.40
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P4,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	7.00
Front-end cycles	10.25
P0 cycles	4.50
P1 cycles	4.00
P2 cycles	10.50
P3 cycles	10.17
P4 cycles	14.00
P5 cycles	1.00
P6 cycles	4.50
P7 cycles	10.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	41.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	11.00
FLOP/cycle	4.57
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	58.29
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	320.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.40
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P4,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	7.00
Front-end cycles	10.25
P0 cycles	4.50
P1 cycles	4.00
P2 cycles	10.50
P3 cycles	10.17
P4 cycles	14.00
P5 cycles	1.00
P6 cycles	4.50
P7 cycles	10.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	41.00
Nb loads	17.00
Nb stores	10.00
Nb stack references	11.00
FLOP/cycle	4.57
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	58.29
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	320.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:52-53.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 10.00 cycles (1.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 10.50 cycles (1.33x speedup).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZGVdN8v_expf@plt: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 496 bytes (124 single precision FP elements). The binary loop is storing 320 bytes (80 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	41
loop length	279
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	11

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.50	4.00	10.50	10.17	14.00	1.00	4.50	10.33
cycles	4.50	4.00	10.50	10.17	14.00	1.00	4.50	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.25
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

27% of peak load performance is reached (35.43 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.86 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM4,0x200(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVAPS %YMM3,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS %YMM2,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS %YMM1,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS (%RDI,%R15,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x20(%RDI,%R15,4),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RDI,%R15,4),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RDI,%R15,4),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x220(%RSP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x1a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VSUBPS %YMM4,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VSUBPS %YMM4,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x1a0(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x1a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x180(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x1e0(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x200(%RSP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x120(%RSP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0xe0(%RSP),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x80(%RSP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
MOV 0x10(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VADDPS 0x1c0(%RSP),%YMM1,%YMM1	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS 0x1a0(%RSP),%YMM2,%YMM2	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS 0x180(%RSP),%YMM3,%YMM3	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM4,%YMM0,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,0x178(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 4ad0 <main+0x24e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:52-53.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

_ZGVdN8v_expf@plt: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 496 bytes (124 single precision FP elements). The binary loop is storing 320 bytes (80 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	41
loop length	279
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	11

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.50	4.00	10.50	10.17	14.00	1.00	4.50	10.33
cycles	4.50	4.00	10.50	10.17	14.00	1.00	4.50	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.25
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

27% of peak load performance is reached (35.43 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (22.86 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4ad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA %YMM4,0x200(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (50.0%)
VMOVAPS %YMM3,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS %YMM2,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS %YMM1,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS (%RDI,%R15,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x20(%RDI,%R15,4),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RDI,%R15,4),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RDI,%R15,4),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x220(%RSP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x1a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VSUBPS %YMM4,%YMM2,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VSUBPS %YMM4,%YMM3,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM1,0x1e0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x1a0(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x1a0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x180(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %YMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x1e0(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
CALL 10d0 <_ZGVdN8v_expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x200(%RSP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x120(%RSP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0xe0(%RSP),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVAPS 0x80(%RSP),%YMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
MOV 0x10(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VADDPS 0x1c0(%RSP),%YMM1,%YMM1	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS 0x1a0(%RSP),%YMM2,%YMM2	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS 0x180(%RSP),%YMM3,%YMM3	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VADDPS %YMM4,%YMM0,%YMM4	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x20,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,0x178(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 4ad0 <main+0x24e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code