OV - attention-avx512 - Loop 31

0x4f60 INC	%R9D

0x4f63 MOV	0x18(%RSP),%R10

0x4f68 CMP	%R10D,%R9D

0x4f6b JE	4f30

0x4f6d MOV	%R9D,%R8D

0x4f70 IMUL	%R10D,%R8D

0x4f74 ADD	%EAX,%R8D

0x4f77 SETB	%R10B

0x4f7b OR	%CL,%R10B

0x4f7e XOR	%R11D,%R11D

0x4f81 JMP	4fa9

  (32) 0x4f90 INC	%R11

  (32) 0x4f93 CMP	0x28(%RSP),%R11

  (32) 0x4f98 MOV	0x48(%RSP),%R13

  (32) 0x4f9d MOV	0x50(%RSP),%R15

  (32) 0x4fa2 MOV	0x20(%RSP),%R12

  (32) 0x4fa7 JE	4f60

  (32) 0x4fa9 CMP	$0x4,%R12D

  (32) 0x4fad JB	4fbe

  (32) 0x4faf MOV	%R11D,%R8D

  (32) 0x4fb2 ADD	%EAX,%R8D

  (32) 0x4fb5 SETB	%R8B

  (32) 0x4fb9 OR	%R10B,%R8B

  (32) 0x4fbc JE	5020

  (32) 0x4fbe XOR	%R15D,%R15D

  (32) 0x4fc1 MOV	0x18(%RSP),%R12

  (32) 0x4fc6 SUB	%R15D,%R12D

  (32) 0x4fc9 MOV	%R15,%R13

  (32) 0x4fcc AND	$0x7,%R12D

  (32) 0x4fd0 JE	4fee

  (32) 0x4fd2 NEG	%R12

  (32) 0x4fd5 XOR	%R8D,%R8D

  (32) 0x4fd8 NOPL	(%RAX,%RAX,1)

    (34) 0x4fe0 DEC	%R8

    (34) 0x4fe3 CMP	%R8,%R12

    (34) 0x4fe6 JNE	4fe0

  (32) 0x4fe8 MOV	%R15,%R13

  (32) 0x4feb SUB	%R8,%R13

  (32) 0x4fee SUB	0x20(%RSP),%R15

  (32) 0x4ff3 CMP	$-0x8,%R15

  (32) 0x4ff7 JA	4f90

  (32) 0x4ff9 MOV	0x20(%RSP),%R8

  (32) 0x4ffe SUB	%R13,%R8

  (32) 0x5001 NOPW	%CS:(%RAX,%RAX,1)

    (33) 0x5010 ADD	$-0x8,%R8

    (33) 0x5014 JNE	5010

  (32) 0x5016 JMP	4f90

  (32) 0x5020 CMP	$0x20,%R12D

  (32) 0x5024 JAE	502b

  (32) 0x5026 XOR	%R12D,%R12D

  (32) 0x5029 JMP	5050

  (32) 0x502b MOV	%RDX,%R8

  (32) 0x502e XCHG	%AX,%AX

    (35) 0x5030 ADD	$-0x20,%R8

    (35) 0x5034 JNE	5030

  (32) 0x5036 CMP	%EDX,%R12D

  (32) 0x5039 JE	4f90

  (32) 0x503f MOV	%RDX,%R12

  (32) 0x5042 MOV	%RDX,%R15

  (32) 0x5045 TESTB	$0x1c,0x18(%RSP)

  (32) 0x504a JE	4fc1

  (32) 0x5050 ADD	%RDI,%R12

  (32) 0x5053 NOPW	%CS:(%RAX,%RAX,1)

    (36) 0x5060 ADD	$0x4,%R12

    (36) 0x5064 JNE	5060

  (32) 0x5066 MOV	%RSI,%R15

  (32) 0x5069 CMP	%ESI,0x20(%RSP)

  (32) 0x506d JE	4f90

  (32) 0x5073 JMP	4fc1

/home/eoseret/Applications/llm-attention/attention.cpp: 26 - 30

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.19
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.91
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.19
Front-end cycles	2.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.91
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-30
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:26-30.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.19 cycles (14.67x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11
nb uops	11
loop length	35
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	0.50	0.50	0.00	2.00	2.00	0.00
cycles	2.00	2.00	0.50	0.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Dispatch	2.00
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

2% of peak load performance is reached (2.91 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 4f6d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x18(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R10D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JE 4f30 <main+0x2940>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %R10D,%R8D	1	0	1	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
SETB %R10B	1	0.50	0	0	0	0	0.50	1	0.50	N/A
OR %CL,%R10B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4fa9 <main+0x29b9>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention.cpp:26-30
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:26-30.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:26.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.19 cycles (14.67x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	11
nb uops	11
loop length	35
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	0.50	0.50	0.00	2.00	2.00	0.00
cycles	2.00	2.00	0.50	0.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Dispatch	2.00
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

2% of peak load performance is reached (2.91 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 4f6d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0x18(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R10D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JE 4f30 <main+0x2940>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %R10D,%R8D	1	0	1	0	0	0	0	3	1	N/A
ADD %EAX,%R8D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
SETB %R10B	1	0.50	0	0	0	0	0.50	1	0.50	N/A
OR %CL,%R10B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4fa9 <main+0x29b9>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code