OV - attention-avx512 - Loop 44

	Loop Id: 44	Module: attention-avx512	Source: attention.cpp:52-53	Coverage: 0.16%

0x6480 VMOVAPS	%YMM2,0x100(%RSP)    [2]

0x6489 VMOVUPS	(%RSI,%RBX,4),%YMM0    [1]

0x648e VSUBPS	0x40(%RSP),%YMM0,%YMM0    [2]

0x6494 VMOVAPS	%YMM0,0x200(%RSP)    [2]

0x649d VEXTRACTF128	$0x1,%YMM0,%XMM0

0x64a3 VMOVAPS	%XMM0,0x180(%RSP)    [2]

0x64ac MOV	%R9,%R15

0x64af VZEROUPPER

0x64b2 CALL	1110 <expf@plt>

0x64b7 VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x64c0 VMOVSHDUP	0x180(%RSP),%XMM0    [2]

0x64c9 CALL	1110 <expf@plt>

0x64ce VMOVAPS	0x80(%RSP),%XMM1    [2]

0x64d7 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x64dd VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x64e6 VPERMILPD	$0x1,0x180(%RSP),%XMM0    [2]

0x64f1 CALL	1110 <expf@plt>

0x64f6 VMOVAPS	0x80(%RSP),%XMM1    [2]

0x64ff VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6505 VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x650e VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [2]

0x6519 CALL	1110 <expf@plt>

0x651e VMOVAPS	0x80(%RSP),%XMM1    [2]

0x6527 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x652d VMOVAPS	%XMM0,0x180(%RSP)    [2]

0x6536 VMOVAPS	0x200(%RSP),%YMM0    [2]

0x653f VZEROUPPER

0x6542 CALL	1110 <expf@plt>

0x6547 VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x6550 VMOVSHDUP	0x200(%RSP),%XMM0    [2]

0x6559 CALL	1110 <expf@plt>

0x655e VMOVAPS	0x80(%RSP),%XMM1    [2]

0x6567 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x656d VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x6576 VPERMILPD	$0x1,0x200(%RSP),%XMM0    [2]

0x6581 CALL	1110 <expf@plt>

0x6586 VMOVAPS	0x80(%RSP),%XMM1    [2]

0x658f VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6595 VMOVAPS	%XMM0,0x80(%RSP)    [2]

0x659e VPERMILPS	$-0x1,0x200(%RSP),%XMM0    [2]

0x65a9 CALL	1110 <expf@plt>

0x65ae VMOVAPS	0x100(%RSP),%YMM2    [2]

0x65b7 MOV	%R15,%R9

0x65ba MOV	0x38(%RSP),%RSI    [2]

0x65bf VMOVAPS	0x80(%RSP),%XMM1    [2]

0x65c8 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x65ce VINSERTF128	$0x1,0x180(%RSP),%YMM0,%YMM0    [2]

0x65d9 VADDPS	%YMM2,%YMM0,%YMM2

0x65dd ADD	$0x8,%RBX

0x65e1 CMP	%RBX,%R15

0x65e4 JNE	6480

/home/eoseret/Applications/llm-attention/attention.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.41
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	5.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P4,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	8
CQA cycles	18.00
CQA cycles if no scalar integer	12.75
CQA cycles if FP arith vectorized	14.63
CQA cycles if fully vectorized	3.55
Front-end cycles	17.25
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	18.00
P5 cycles	11.00
P6 cycles	8.00
P7 cycles	12.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	69.00
Nb loads	18.00
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	0.89
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.78
Bytes prefetched	0.00
Bytes loaded	344.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.58
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.33
Vector-efficiency ratio all	25.66
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.41
CQA speedup if FP arith vectorized	1.23
CQA speedup if fully vectorized	5.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P4,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	8
CQA cycles	18.00
CQA cycles if no scalar integer	12.75
CQA cycles if FP arith vectorized	14.63
CQA cycles if fully vectorized	3.55
Front-end cycles	17.25
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	18.00
P5 cycles	11.00
P6 cycles	8.00
P7 cycles	12.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	69.00
Nb loads	18.00
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	0.89
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.78
Bytes prefetched	0.00
Bytes loaded	344.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.58
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.33
Vector-efficiency ratio all	25.66
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:52-53.

It is intermediate loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 12.75 cycles (1.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VPERMILPD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VPERMILPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VZEROUPPER: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VINSERTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 344 bytes (86 single precision FP elements). The binary loop is storing 192 bytes (48 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	69
loop length	362
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.25 cycles
front end	17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	12.00	12.00	18.00	11.00	8.00	12.00
cycles	2.50	2.50	12.00	12.00	18.00	11.00	8.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.25
Dispatch	18.00
Data deps.	1.00
Overall L1	18.00

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	26%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	25%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

14% of peak load performance is reached (19.11 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM2,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS (%RSI,%RBX,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS 0x40(%RSP),%YMM0,%YMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM0,0x200(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x200(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x200(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x180(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VADDPS %YMM2,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 6480 <main+0x2cd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:52-53.

It is intermediate loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 8 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VPERMILPD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VPERMILPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VZEROUPPER: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53
VINSERTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 344 bytes (86 single precision FP elements). The binary loop is storing 192 bytes (48 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	69
loop length	362
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	17.25 cycles
front end	17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	12.00	12.00	18.00	11.00	8.00	12.00
cycles	2.50	2.50	12.00	12.00	18.00	11.00	8.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.25
Dispatch	18.00
Data deps.	1.00
Overall L1	18.00

Vectorization ratios

INT

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	26%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	25%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

14% of peak load performance is reached (19.11 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.67 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM2,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS (%RSI,%RBX,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS 0x40(%RSP),%YMM0,%YMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPS %YMM0,0x200(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x200(%RSP),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x200(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%YMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x180(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VADDPS %YMM2,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 6480 <main+0x2cd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code