OV - attention-avx512 - Loop 43

	Loop Id: 43	Module: attention-avx512	Source: attention.cpp:55-56	Coverage: 0.68%

0x69e0 VMOVUPS	(%RSI,%RBX,4),%XMM0    [3]

0x69e5 VSUBPS	0x2c0(%RSP),%XMM0,%XMM0    [2]

0x69ee VMOVAPS	%XMM0,0x180(%RSP)    [2]

0x69f7 MOV	%RDX,%R12

0x69fa VZEROUPPER

0x69fd CALL	1110 <expf@plt>

0x6a02 VMOVAPS	%XMM0,0x100(%RSP)    [2]

0x6a0b VMOVSHDUP	0x180(%RSP),%XMM0    [2]

0x6a14 CALL	1110 <expf@plt>

0x6a19 VMOVAPS	0x100(%RSP),%XMM1    [2]

0x6a22 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6a28 VMOVAPS	%XMM0,0x100(%RSP)    [2]

0x6a31 VPERMILPD	$0x1,0x180(%RSP),%XMM0    [2]

0x6a3c CALL	1110 <expf@plt>

0x6a41 VMOVAPS	0x100(%RSP),%XMM1    [2]

0x6a4a VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6a50 VMOVAPS	%XMM0,0x100(%RSP)    [2]

0x6a59 VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [2]

0x6a64 CALL	1110 <expf@plt>

0x6a69 MOV	%R12,%RDX

0x6a6c MOV	0x38(%RSP),%RSI    [2]

0x6a71 VMOVAPS	0x100(%RSP),%XMM1    [2]

0x6a7a VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6a80 VDIVPS	0x40(%RSP),%XMM0,%XMM0    [2]

0x6a86 VMOVUPS	%XMM0,(%R12,%RBX,4)    [1]

0x6a8c ADD	$0x4,%RBX

0x6a90 CMP	%RBX,0x80(%RSP)    [2]

0x6a98 JNE	69e0

/home/eoseret/Applications/llm-attention/attention.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.42
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue, P4,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.35
CQA cycles if fully vectorized	3.00
Front-end cycles	9.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.83
P3 cycles	6.50
P4 cycles	9.00
P5 cycles	5.00
P6 cycles	4.00
P7 cycles	6.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	36.00
Nb loads	11.00
Nb stores	5.00
Nb stack references	6.00
FLOP/cycle	0.89
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	78.95
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	20.72
Vector-efficiency ratio load	23.61
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	15.18

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.42
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	micro-operation queue, P4,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	9.00
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.35
CQA cycles if fully vectorized	3.00
Front-end cycles	9.00
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.83
P3 cycles	6.50
P4 cycles	9.00
P5 cycles	5.00
P6 cycles	4.00
P7 cycles	6.67
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	36.00
Nb loads	11.00
Nb stores	5.00
Nb stack references	6.00
FLOP/cycle	0.89
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	80.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	78.95
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	20.72
Vector-efficiency ratio load	23.61
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	15.18

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is intermediate loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 6.25 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

78% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 6.83 cycles (1.32x speedup).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPERMILPD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: divide

The binary loop is loading 160 bytes (40 single precision FP elements). The binary loop is storing 80 bytes (20 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	36
loop length	190
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	6.83	6.50	9.00	5.00	4.00	6.67
cycles	2.00	2.00	6.83	6.50	9.00	5.00	4.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	9.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	40%

INT+FP

all	78%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	42%

Vector efficiency ratios

INT

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	20%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	13%

INT+FP

all	20%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

13% of peak load performance is reached (17.78 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.89 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 6.83 cycles (1.32x speedup).

ASM code

In the binary file, the address of the loop is: 69e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VSUBPS 0x2c0(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VDIVPS 0x40(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	vect (25.0%)
VMOVUPS %XMM0,(%R12,%RBX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
ADD $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,0x80(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 69e0 <main+0x3230>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is intermediate loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 6.25 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

78% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPERMILPD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: divide

The binary loop is loading 160 bytes (40 single precision FP elements). The binary loop is storing 80 bytes (20 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	36
loop length	190
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	6.83	6.50	9.00	5.00	4.00	6.67
cycles	2.00	2.00	6.83	6.50	9.00	5.00	4.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.00
Dispatch	9.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	40%

INT+FP

all	78%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	42%

Vector efficiency ratios

INT

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	20%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	13%

INT+FP

all	20%
load	23%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

13% of peak load performance is reached (17.78 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (8.89 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 69e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VSUBPS 0x2c0(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VDIVPS 0x40(%RSP),%XMM0,%XMM0	1	1	0	0.50	0.50	0	0	0	0	11	3	vect (25.0%)
VMOVUPS %XMM0,(%R12,%RBX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
ADD $0x4,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,0x80(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 69e0 <main+0x3230>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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General properties

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Cycles summary

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Cycles and memory resources usage

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ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code