OV - attention-avx512 - Loop 39

	Loop Id: 39	Module: attention-avx512	Source: attention.cpp:55-56	Coverage: 2.73%

0x66f0 VMOVUPS	(%RSI,%RBX,4),%ZMM0    [2]

0x66f7 VSUBPS	0x300(%RSP),%ZMM0,%ZMM0    [3]

0x66ff VMOVAPS	%ZMM0,0x180(%RSP)    [3]

0x6707 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x670e VMOVAPS	%XMM0,0x100(%RSP)    [3]

0x6717 VZEROUPPER

0x671a CALL	1110 <expf@plt>

0x671f VMOVAPS	%XMM0,0x80(%RSP)    [3]

0x6728 VMOVSHDUP	0x100(%RSP),%XMM0    [3]

0x6731 CALL	1110 <expf@plt>

0x6736 VMOVAPS	0x80(%RSP),%XMM1    [3]

0x673f VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6745 VMOVAPS	%XMM0,0x80(%RSP)    [3]

0x674e VPERMILPD	$0x1,0x100(%RSP),%XMM0    [3]

0x6759 CALL	1110 <expf@plt>

0x675e VMOVAPS	0x80(%RSP),%XMM1    [3]

0x6767 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x676d VMOVAPS	%XMM0,0x80(%RSP)    [3]

0x6776 VPERMILPS	$-0x1,0x100(%RSP),%XMM0    [3]

0x6781 CALL	1110 <expf@plt>

0x6786 VMOVAPS	0x80(%RSP),%XMM1    [3]

0x678f VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6795 VMOVAPS	%XMM0,0x80(%RSP)    [3]

0x679e VMOVAPS	0x180(%RSP),%ZMM0    [3]

0x67a6 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x67ad VMOVAPS	%XMM0,0x100(%RSP)    [3]

0x67b6 VZEROUPPER

0x67b9 CALL	1110 <expf@plt>

0x67be VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x67c4 VMOVSHDUP	0x100(%RSP),%XMM0    [3]

0x67cd CALL	1110 <expf@plt>

0x67d2 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x67d8 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x67de VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x67e4 VPERMILPD	$0x1,0x100(%RSP),%XMM0    [3]

0x67ef CALL	1110 <expf@plt>

0x67f4 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x67fa VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6800 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x6806 VPERMILPS	$-0x1,0x100(%RSP),%XMM0    [3]

0x6811 CALL	1110 <expf@plt>

0x6816 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x681c VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6822 VINSERTF128	$0x1,0x80(%RSP),%YMM0,%YMM0    [3]

0x682d VMOVAPS	%YMM0,0x80(%RSP)    [3]

0x6836 VMOVAPS	0x180(%RSP),%ZMM0    [3]

0x683e VEXTRACTF128	$0x1,%YMM0,%XMM0

0x6844 VMOVAPS	%XMM0,0x100(%RSP)    [3]

0x684d VZEROUPPER

0x6850 CALL	1110 <expf@plt>

0x6855 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x685b VMOVSHDUP	0x100(%RSP),%XMM0    [3]

0x6864 CALL	1110 <expf@plt>

0x6869 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x686f VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6875 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x687b VPERMILPD	$0x1,0x100(%RSP),%XMM0    [3]

0x6886 CALL	1110 <expf@plt>

0x688b VMOVAPS	0x40(%RSP),%XMM1    [3]

0x6891 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6897 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x689d VPERMILPS	$-0x1,0x100(%RSP),%XMM0    [3]

0x68a8 CALL	1110 <expf@plt>

0x68ad VMOVAPS	0x40(%RSP),%XMM1    [3]

0x68b3 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x68b9 VMOVAPS	%XMM0,0x100(%RSP)    [3]

0x68c2 VMOVAPS	0x180(%RSP),%ZMM0    [3]

0x68ca VZEROUPPER

0x68cd CALL	1110 <expf@plt>

0x68d2 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x68d8 VMOVSHDUP	0x180(%RSP),%XMM0    [3]

0x68e1 CALL	1110 <expf@plt>

0x68e6 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x68ec VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x68f2 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x68f8 VPERMILPD	$0x1,0x180(%RSP),%XMM0    [3]

0x6903 CALL	1110 <expf@plt>

0x6908 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x690e VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6914 VMOVAPS	%XMM0,0x40(%RSP)    [3]

0x691a VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [3]

0x6925 CALL	1110 <expf@plt>

0x692a MOV	0x1f8(%RSP),%RDX    [3]

0x6932 MOV	0x38(%RSP),%RSI    [3]

0x6937 VMOVAPS	0x40(%RSP),%XMM1    [3]

0x693d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6943 VINSERTF128	$0x1,0x100(%RSP),%YMM0,%YMM0    [3]

0x694e VINSERTF64X4	$0x1,0x80(%RSP),%ZMM0,%ZMM0    [3]

0x6957 VDIVPS	0x2c0(%RSP),%ZMM0,%ZMM0    [3]

0x695f VMOVUPS	%ZMM0,(%RDX,%RBX,4)    [1]

0x6966 ADD	$0x10,%RBX

0x696a CMP	%RBX,%R12

0x696d JNE	66f0

/home/eoseret/Applications/llm-attention/attention.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P4,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	36.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	22.75
Front-end cycles	33.50
P0 cycles	5.00
P1 cycles	4.00
P2 cycles	23.83
P3 cycles	23.50
P4 cycles	36.00
P5 cycles	23.00
P6 cycles	16.00
P7 cycles	23.67
DIV/SQRT cycles	10.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	134.00
Nb loads	35.00
Nb stores	20.00
Nb stack references	8.00
FLOP/cycle	0.89
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.56
Bytes prefetched	0.00
Bytes loaded	848.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P4,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	36.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	22.75
Front-end cycles	33.50
P0 cycles	5.00
P1 cycles	4.00
P2 cycles	23.83
P3 cycles	23.50
P4 cycles	36.00
P5 cycles	23.00
P6 cycles	16.00
P7 cycles	23.67
DIV/SQRT cycles	10.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	134.00
Nb loads	35.00
Nb stores	20.00
Nb stack references	8.00
FLOP/cycle	0.89
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.56
Bytes prefetched	0.00
Bytes loaded	848.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 36.00 to 25.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 36.00 to 22.75 cycles (1.58x speedup).

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 36.00 to 33.50 cycles (1.07x speedup).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 16 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPD: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPS: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VZEROUPPER: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VEXTRACTF32X4: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 848 bytes (212 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	134
loop length	643
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	33.50 cycles
front end	33.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	4.00	23.83	23.50	36.00	23.00	16.00	23.67
cycles	5.00	4.00	23.83	23.50	36.00	23.00	16.00	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.50
Dispatch	36.00
DIV/SQRT	10.00
Data deps.	1.00
Overall L1	36.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	53%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	17%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

18% of peak load performance is reached (23.56 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 66f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VSUBPS 0x300(%RSP),%ZMM0,%ZMM0	1	0.50	0	0.50	0.50	0	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x80(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VMOVAPS %YMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0x1f8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x100(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VINSERTF64X4 $0x1,0x80(%RSP),%ZMM0,%ZMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (50.0%)
VDIVPS 0x2c0(%RSP),%ZMM0,%ZMM0	4	2.50	0	0.50	0.50	0	0.50	0	0	18	10	vect (100.0%)
VMOVUPS %ZMM0,(%RDX,%RBX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (100.0%)
ADD $0x10,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,%R12	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 66f0 <main+0x2f40>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 16 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPD: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VPERMILPS: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VZEROUPPER: 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VEXTRACTF32X4: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56
- /home/eoseret/Applications/llm-attention/attention.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 848 bytes (212 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	134
loop length	643
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	33.50 cycles
front end	33.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	4.00	23.83	23.50	36.00	23.00	16.00	23.67
cycles	5.00	4.00	23.83	23.50	36.00	23.00	16.00	23.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	33.50
Dispatch	36.00
DIV/SQRT	10.00
Data deps.	1.00
Overall L1	36.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	53%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	17%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

18% of peak load performance is reached (23.56 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (12.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 66f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RBX,4),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VSUBPS 0x300(%RSP),%ZMM0,%ZMM0	1	0.50	0	0.50	0.50	0	0.50	0	0	4	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x180(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x80(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x80(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VMOVAPS %YMM0,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x100(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVAPS 0x180(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (12.5%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	2	0	0	0.50	0.50	0	1	0	0	1	1	vect (25.0%)
CALL 1110 <expf@plt>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0x1f8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x38(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x100(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (25.0%)
VINSERTF64X4 $0x1,0x80(%RSP),%ZMM0,%ZMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	5	0.50	vect (50.0%)
VDIVPS 0x2c0(%RSP),%ZMM0,%ZMM0	4	2.50	0	0.50	0.50	0	0.50	0	0	18	10	vect (100.0%)
VMOVUPS %ZMM0,(%RDX,%RBX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (100.0%)
ADD $0x10,%RBX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %RBX,%R12	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 66f0 <main+0x2f40>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code