OV - attention-avx512 - Loop 32

	Loop Id: 32	Module: attention-avx512	Source: attention.cpp:27-31	Coverage: 0.78%

0x6c90 INC	%R11

0x6c93 CMP	0x68(%RSP),%R11

0x6c98 MOV	0xd8(%RSP),%RBX

0x6ca0 MOV	0x70(%RSP),%R15

0x6ca5 JE	6c60

0x6ca7 CMP	$0x4,%R15D

0x6cab JB	6cba

0x6cad MOV	%R11D,%EBX

0x6cb0 ADD	%EAX,%EBX

0x6cb2 SETB	%BL

0x6cb5 OR	%R10B,%BL

0x6cb8 JE	6cf0

0x6cba XOR	%EBX,%EBX

0x6cbc MOV	%RBX,%R15

0x6cbf OR	$0x1,%R15

0x6cc3 TEST	$0x1,%R13B

0x6cc7 JE	6ccc

0x6cc9 MOV	%R15,%RBX

0x6ccc CMP	%R15D,0x70(%RSP)

0x6cd1 JE	6c90

0x6cd3 MOV	0x70(%RSP),%R15

0x6cd8 SUB	%RBX,%R15

0x6cdb NOPL	(%RAX,%RAX,1)

  (33) 0x6ce0 ADD	$-0x2,%R15

  (33) 0x6ce4 JNE	6ce0

0x6ce6 JMP	6c90

0x6cf0 CMP	$0x20,%R15D

0x6cf4 JAE	6cfe

0x6cf6 XOR	%R15D,%R15D

0x6cf9 JMP	6db0

0x6cfe VXORPS	%XMM0,%XMM0,%XMM0

0x6d02 XOR	%EBX,%EBX

0x6d04 VPXOR	%XMM1,%XMM1,%XMM1

0x6d08 VPXOR	%XMM2,%XMM2,%XMM2

0x6d0c VPXOR	%XMM3,%XMM3,%XMM3

0x6d10 MOV	0x178(%RSP),%R13

0x6d18 MOV	0xd0(%RSP),%RDI

  (34) 0x6d20 LEA	(%R8,%RBX,1),%R15D

  (34) 0x6d24 VCVTPS2PD	(%RDI,%R15,4),%ZMM4

  (34) 0x6d2b VCVTPS2PD	0x20(%RDI,%R15,4),%ZMM5

  (34) 0x6d33 VCVTPS2PD	0x40(%RDI,%R15,4),%ZMM6

  (34) 0x6d3b VCVTPS2PD	0x60(%RDI,%R15,4),%ZMM7

  (34) 0x6d43 LEA	(%R11,%RBX,1),%R15D

  (34) 0x6d47 VCVTPS2PD	(%R13,%R15,4),%ZMM8

  (34) 0x6d4f VCVTPS2PD	0x20(%R13,%R15,4),%ZMM9

  (34) 0x6d57 VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

  (34) 0x6d5d VCVTPS2PD	0x40(%R13,%R15,4),%ZMM4

  (34) 0x6d65 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

  (34) 0x6d6b VCVTPS2PD	0x60(%R13,%R15,4),%ZMM5

  (34) 0x6d73 VFMADD231PD	%ZMM4,%ZMM6,%ZMM2

  (34) 0x6d79 VFMADD231PD	%ZMM5,%ZMM7,%ZMM3

  (34) 0x6d7f ADD	$0x20,%RBX

  (34) 0x6d83 CMP	%RBX,%RDX

  (34) 0x6d86 JNE	6d20

0x6d88 CMP	%EDX,0x70(%RSP)

0x6d8c MOV	0x60(%RSP),%R13

0x6d91 JE	6c90

0x6d97 MOV	%RDX,%R15

0x6d9a MOV	%RDX,%RBX

0x6d9d TEST	$0x1c,%R13B

0x6da1 JE	6cbc

0x6da7 NOPW	(%RAX,%RAX,1)

  (35) 0x6db0 ADD	$0x4,%R15

  (35) 0x6db4 CMP	%R15,%RSI

  (35) 0x6db7 JNE	6db0

0x6db9 MOV	%RSI,%RBX

0x6dbc CMP	%ESI,0x70(%RSP)

0x6dc0 JE	6c90

0x6dc6 JMP	6cbc

/home/eoseret/Applications/llm-attention/attention.cpp: 27 - 31

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-avx512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.61
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	23.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.81
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	0.51
Front-end cycles	11.75
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	6.50
P6 cycles	6.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.79
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	21.05
Vector-efficiency ratio all	11.89
Vector-efficiency ratio load	11.11
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	10.42
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.92

Metric	Value
CQA speedup if no scalar integer	2.61
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	23.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.81
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:27-27,attention.cpp:30-30
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	0.51
Front-end cycles	11.75
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	6.50
P6 cycles	6.50
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.79
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	21.05
Vector-efficiency ratio all	11.89
Vector-efficiency ratio load	11.11
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	10.42
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:27-31
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27-31.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27,30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 4.50 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.75 to 0.51 cycles (23.14x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	47
nb uops	47
loop length	188
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.50	5.00	5.00	0.00	6.50	6.50	0.00
cycles	6.50	6.50	5.00	5.00	0.00	6.50	6.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	6.50
Overall L1	11.75

Vectorization ratios

INT

all	11%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

4% of peak load performance is reached (5.79 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.75 to 6.50 cycles (1.81x speedup).

ASM code

In the binary file, the address of the loop is: 6ca7

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0x68(%RSP),%R11	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
MOV 0xd8(%RSP),%RBX	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0x70(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 6c60 <main+0x34b0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
CMP $0x4,%R15D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JB 6cba <main+0x350a>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
ADD %EAX,%EBX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
SETB %BL	1	0.50	0	0	0	0	0.50	1	0.50	N/A
OR %R10B,%BL	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6cf0 <main+0x3540>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
OR $0x1,%R15	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (1.6%)
TEST $0x1,%R13B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6ccc <main+0x351c>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %R15D,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (6.3%)
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x70(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
SUB %RBX,%R15	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 6c90 <main+0x34e0>	1	0	0	0	0	0	1	0	1-2	N/A
CMP $0x20,%R15D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 6cfe <main+0x354e>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 6db0 <main+0x3600>	1	0	0	0	0	0	1	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x178(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %EDX,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (6.3%)
MOV 0x60(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0x1c,%R13B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6cbc <main+0x350c>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
JMP 6cbc <main+0x350c>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention.cpp:27-31
Module	attention-avx512

The loop is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27-31.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention.cpp:27,30.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 4.50 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	47
nb uops	47
loop length	188
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.50	6.50	5.00	5.00	0.00	6.50	6.50	0.00
cycles	6.50	6.50	5.00	5.00	0.00	6.50	6.50	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	6.50
Overall L1	11.75

Vectorization ratios

INT

all	11%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

4% of peak load performance is reached (5.79 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6ca7

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %R11	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0x68(%RSP),%R11	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
MOV 0xd8(%RSP),%RBX	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0x70(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 6c60 <main+0x34b0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
CMP $0x4,%R15D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JB 6cba <main+0x350a>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
ADD %EAX,%EBX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
SETB %BL	1	0.50	0	0	0	0	0.50	1	0.50	N/A
OR %R10B,%BL	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6cf0 <main+0x3540>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
OR $0x1,%R15	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (1.6%)
TEST $0x1,%R13B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6ccc <main+0x351c>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R15,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %R15D,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (6.3%)
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x70(%RSP),%R15	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
SUB %RBX,%R15	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 6c90 <main+0x34e0>	1	0	0	0	0	0	1	0	1-2	N/A
CMP $0x20,%R15D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 6cfe <main+0x354e>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 6db0 <main+0x3600>	1	0	0	0	0	0	1	0	1-2	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV 0x178(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %EDX,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (6.3%)
MOV 0x60(%RSP),%R13	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0x1c,%R13B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 6cbc <main+0x350c>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
CMP %ESI,0x70(%RSP)	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
JE 6c90 <main+0x34e0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
JMP 6cbc <main+0x350c>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code