OV - attention-icx-skl512 - Loop 51

	Loop Id: 51	Module: attention-icx-skl512	Source: attention_v2.cpp:163-163 [...]	Coverage: 0.83%

0x403d90 MOV	0x4f8(%RSP,%RDX,8),%RSI

0x403d98 INC	%RDX

0x403d9b MOV	%RSI,%RDI

0x403d9e SHR	$0xb,%RDI

0x403da2 MOV	%EDI,%EDI

0x403da4 XOR	%RSI,%RDI

0x403da7 MOV	%EDI,%ESI

0x403da9 SAL	$0x7,%ESI

0x403dac AND	$-0x62d3a980,%ESI

0x403db2 XOR	%RDI,%RSI

0x403db5 MOV	%ESI,%EDI

0x403db7 SAL	$0xf,%EDI

0x403dba AND	$-0x103a0000,%EDI

0x403dc0 XOR	%RSI,%RDI

0x403dc3 MOV	%RDI,%RSI

0x403dc6 SHR	$0x12,%RSI

0x403dca XOR	%EDI,%ESI

0x403dcc VCVTUSI2SS	%ESI,%XMM13,%XMM0

0x403dd2 VMULSS	%XMM0,%XMM11,%XMM0

0x403dd6 VUCOMISS	%XMM12,%XMM0

0x403ddb JB	403fa1

0x403de1 CMP	$0x270,%RDX

0x403de8 JB	403d90

0x403dea XOR	%EDX,%EDX

0x403dec NOPL	(%RAX)

  (52) 0x403df0 VMOVDQU	0x500(%RSP,%RDX,1),%YMM0

  (52) 0x403df9 VPSRLQ	$0x1,%YMM0,%YMM1

  (52) 0x403dfe VPAND	%YMM3,%YMM1,%YMM1

  (52) 0x403e02 VPBROADCASTQ	%RAX,%YMM2

  (52) 0x403e08 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

  (52) 0x403e0e VPSRLQ	$0x1,%YMM2,%YMM2

  (52) 0x403e13 VPERMQ	$-0x6d,%YMM2,%YMM2

  (52) 0x403e19 VPAND	%YMM4,%YMM2,%YMM2

  (52) 0x403e1d VPTERNLOGQ	$0x56,0x1160(%RSP,%RDX,1),%YMM1,%YMM2

  (52) 0x403e29 VPTESTMQ	%YMM5,%YMM0,%K1

  (52) 0x403e2f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

  (52) 0x403e35 VMOVDQU	%YMM2,0x4f8(%RSP,%RDX,1)

  (52) 0x403e3e MOV	0x518(%RSP,%RDX,1),%RAX

  (52) 0x403e46 ADD	$0x20,%RDX

  (52) 0x403e4a CMP	$0x700,%RDX

  (52) 0x403e51 JNE	403df0

0x403e53 MOV	0xc08(%RSP),%RDX

0x403e5b VMOVDQU	0xc00(%RSP),%XMM1

0x403e64 VPSRLQ	$0x1,%XMM1,%XMM2

0x403e69 VPAND	%XMM7,%XMM2,%XMM2

0x403e6d VEXTRACTI128	$0x1,%YMM0,%XMM0

0x403e73 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

0x403e79 VPSRLQ	$0x1,%XMM0,%XMM0

0x403e7e VPAND	%XMM0,%XMM8,%XMM0

0x403e82 VPTERNLOGQ	$0x56,0x1860(%RSP),%XMM2,%XMM0

0x403e8e VPTESTMQ	%XMM9,%XMM1,%K1

0x403e94 VPXORQ	%XMM10,%XMM0,%XMM0{%K1}

0x403e9a VMOVDQU	%XMM0,0xbf8(%RSP)

0x403ea3 MOV	0xc10(%RSP),%RAX

0x403eab MOV	%EAX,%ESI

0x403ead SHR	$0x1,%ESI

0x403eaf AND	$0x3fffffff,%ESI

0x403eb5 SHR	$0x1,%RDX

0x403eb8 AND	$-0x40000000,%RDX

0x403ebf OR	%RSI,%RDX

0x403ec2 XOR	0x1870(%RSP),%RDX

0x403eca MOV	%EAX,%ESI

0x403ecc AND	$0x1,%ESI

0x403ecf NEG	%ESI

0x403ed1 AND	$-0x66f74f21,%ESI

0x403ed7 XOR	%RDX,%RSI

0x403eda MOV	%RSI,0xc08(%RSP)

0x403ee2 XOR	%EDX,%EDX

0x403ee4 NOPW	%CS:(%RAX,%RAX,1)

  (53) 0x403ef0 VMOVDQU	0xc18(%RSP,%RDX,1),%YMM0

  (53) 0x403ef9 VPSRLQ	$0x1,%YMM0,%YMM1

  (53) 0x403efe VPAND	%YMM3,%YMM1,%YMM1

  (53) 0x403f02 VPBROADCASTQ	%RAX,%YMM2

  (53) 0x403f08 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

  (53) 0x403f0e VPSRLQ	$0x1,%YMM2,%YMM2

  (53) 0x403f13 VPERMQ	$-0x6d,%YMM2,%YMM2

  (53) 0x403f19 VPAND	%YMM4,%YMM2,%YMM2

  (53) 0x403f1d VPTERNLOGQ	$0x56,0x4f8(%RSP,%RDX,1),%YMM1,%YMM2

  (53) 0x403f29 VPTESTMQ	%YMM5,%YMM0,%K1

  (53) 0x403f2f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

  (53) 0x403f35 VMOVDQU	%YMM2,0xc10(%RSP,%RDX,1)

  (53) 0x403f3e MOV	0xc30(%RSP,%RDX,1),%RAX

  (53) 0x403f46 ADD	$0x20,%RDX

  (53) 0x403f4a CMP	$0xc60,%RDX

  (53) 0x403f51 JNE	403ef0

0x403f53 MOV	0x1870(%RSP),%RDX

0x403f5b AND	%R9,%RDX

0x403f5e MOV	0x4f8(%RSP),%RAX

0x403f66 MOV	%EAX,%ESI

0x403f68 AND	$0x7ffffffe,%ESI

0x403f6e OR	%RDX,%RSI

0x403f71 SHR	$0x1,%RSI

0x403f74 XOR	0x1158(%RSP),%RSI

0x403f7c MOV	%EAX,%EDX

0x403f7e AND	$0x1,%EDX

0x403f81 NEG	%EDX

0x403f83 AND	$-0x66f74f21,%EDX

0x403f89 XOR	%RSI,%RDX

0x403f8c MOV	%RDX,0x1870(%RSP)

0x403f94 MOV	$0x1,%EDX

0x403f99 MOV	%RAX,%RSI

0x403f9c JMP	403d9b

0x403fa1 VMOVSS	%XMM0,(%RBX,%RCX,4)

0x403fa6 INC	%RCX

0x403fa9 CMP	0xb0(%RSP),%RCX

0x403fb1 JNE	403de1

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 163 - 163

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.23
CQA speedup if FP arith vectorized	1.80
CQA speedup if fully vectorized	10.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	3.88
CQA cycles if FP arith vectorized	6.94
CQA cycles if fully vectorized	1.15
Front-end cycles	12.50
P0 cycles	8.63
P1 cycles	8.63
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.50
P5 cycles	8.63
P6 cycles	8.63
P7 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.50
Nb uops	50.00
Nb loads	5.50
Nb stores	2.50
Nb stack references	5.00
FLOP/cycle	0.08
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.88
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	20.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	8.06
Vectorization ratio load	16.67
Vectorization ratio store	12.50
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.41
Vector-efficiency ratio all	10.31
Vector-efficiency ratio load	14.58
Vector-efficiency ratio store	10.16
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.19

Metric	Value
CQA speedup if no scalar integer	3.48
CQA speedup if FP arith vectorized	1.68
CQA speedup if fully vectorized	10.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25
CQA cycles if no scalar integer	5.25
CQA cycles if FP arith vectorized	10.88
CQA cycles if fully vectorized	1.82
Front-end cycles	18.25
P0 cycles	12.25
P1 cycles	12.25
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	4.00
P5 cycles	12.25
P6 cycles	12.25
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	73.00
Nb loads	9.00
Nb stores	4.00
Nb stack references	9.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.79
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	36.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	16.13
Vectorization ratio load	33.33
Vectorization ratio store	25.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.81
Vector-efficiency ratio all	11.69
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	14.06
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.34

Metric	Value
CQA speedup if no scalar integer	2.70
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	13.94
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.48
Front-end cycles	6.75
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.15
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.96
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.03

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

8% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
12% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPTERNLOGQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 52 bytes (13 single precision FP elements). The binary loop is storing 20 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	49.50
nb uops	50
loop length	227
used x86 registers	7
used mmx registers	0
used xmm registers	7
used ymm registers	0.50
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.63	8.63	2.75	2.75	2.50	8.63	8.63	2.50
cycles	8.63	8.63	2.75	2.75	2.50	8.63	8.63	2.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	12.50
Dispatch	8.63
Data deps.	1.00
Overall L1	12.50

Vectorization ratios

INT

all	8%
load	16%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	8%
load	16%
store	12%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	10%
load	14%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	14%
store	10%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

2% of peak load performance is reached (3.60 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 5.25 cycles (3.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VPTERNLOGQ: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:408

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 88 bytes (22 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	72
nb uops	73
loop length	342
used x86 registers	8
used mmx registers	0
used xmm registers	10
used ymm registers	1
used zmm registers	0
nb stack references	9

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	18.25 cycles
front end	18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.25	12.25	4.50	4.50	4.00	12.25	12.25	4.00
cycles	12.25	12.25	4.50	4.50	4.00	12.25	12.25	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	18.25
Dispatch	12.25
Data deps.	1.00
Overall L1	18.25

Vectorization ratios

INT

all	16%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	16%
load	33%
store	25%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	11%
load	16%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	11%
load	16%
store	14%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.25 cycles. At this rate:

3% of peak load performance is reached (4.82 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.97 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.25 to 12.25 cycles (1.49x speedup).

ASM code

In the binary file, the address of the loop is: 403de1

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x7,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%EDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %EDI,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VCVTUSI2SS %ESI,%XMM13,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS %XMM0,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS %XMM12,%XMM0	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JB 403fa1 <main+0xcf1>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 403d90 <main+0xae0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc08(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
VMOVDQU 0xc00(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPAND %XMM7,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPALIGNR $0x8,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPAND %XMM0,%XMM8,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1860(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (25.0%)
VPTESTMQ %XMM9,%XMM1,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM0,%XMM0{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xbf8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (25.0%)
MOV 0xc10(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $0x3fffffff,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
AND $-0x40000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
OR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
XOR 0x1870(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND $-0x66f74f21,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xc08(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1870(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
AND %R9,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x4f8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1158(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND $-0x66f74f21,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDX,0x1870(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 403d9b <main+0xaeb>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%RBX,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0xb0(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 403de1 <main+0xb31>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 2.50 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 0.48 cycles (13.94x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 16 bytes (4 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	27
loop length	112
used x86 registers	6
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	5.00	1.00	1.00	1.00	5.00	5.00	1.00
cycles	5.00	5.00	1.00	1.00	1.00	5.00	5.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Dispatch	5.00
Data deps.	1.00
Overall L1	6.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	12%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

1% of peak load performance is reached (2.37 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.59 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 403de1

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x4f8(%RSP,%RDX,8),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
INC %RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x7,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%EDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %EDI,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VCVTUSI2SS %ESI,%XMM13,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS %XMM0,%XMM11,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS %XMM12,%XMM0	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JB 403fa1 <main+0xcf1>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 403d90 <main+0xae0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVSS %XMM0,(%RBX,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0xb0(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 403de1 <main+0xb31>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

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512-bits vectorization

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Masked instructions

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Complex instructions

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Slow data structures access

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks