OV - attention-icx-skl512 - Loop 45

	Loop Id: 45	Module: attention-icx-skl512	Source: random.tcc:404-3558 [...]	Coverage: 0.33%

0x404330 MOV	0x4f8(%RSP,%RDX,8),%RSI

0x404338 INC	%RDX

0x40433b MOV	%RSI,%RDI

0x40433e SHR	$0xb,%RDI

0x404342 MOV	%EDI,%EDI

0x404344 XOR	%RSI,%RDI

0x404347 MOV	%EDI,%ESI

0x404349 SAL	$0x7,%ESI

0x40434c AND	$-0x62d3a980,%ESI

0x404352 XOR	%RDI,%RSI

0x404355 MOV	%ESI,%EDI

0x404357 SAL	$0xf,%EDI

0x40435a AND	$-0x103a0000,%EDI

0x404360 XOR	%RSI,%RDI

0x404363 MOV	%RDI,%RSI

0x404366 SHR	$0x12,%RSI

0x40436a XOR	%EDI,%ESI

0x40436c VCVTUSI2SS	%ESI,%XMM25,%XMM0

0x404372 VMULSS	%XMM17,%XMM0,%XMM0

0x404378 VUCOMISS	%XMM18,%XMM0

0x40437e JB	404550

0x404384 CMP	$0x270,%RDX

0x40438b JB	404330

0x40438d XOR	%EDX,%EDX

0x40438f NOP

  (46) 0x404390 VMOVDQU	0x500(%RSP,%RDX,1),%YMM0

  (46) 0x404399 VPSRLQ	$0x1,%YMM0,%YMM1

  (46) 0x40439e VPAND	%YMM3,%YMM1,%YMM1

  (46) 0x4043a2 VPBROADCASTQ	%RAX,%YMM2

  (46) 0x4043a8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

  (46) 0x4043ae VPSRLQ	$0x1,%YMM2,%YMM2

  (46) 0x4043b3 VPERMQ	$-0x6d,%YMM2,%YMM2

  (46) 0x4043b9 VPAND	%YMM4,%YMM2,%YMM2

  (46) 0x4043bd VPTERNLOGQ	$0x56,0x1160(%RSP,%RDX,1),%YMM1,%YMM2

  (46) 0x4043c9 VPTESTMQ	%YMM5,%YMM0,%K1

  (46) 0x4043cf VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

  (46) 0x4043d5 VMOVDQU	%YMM2,0x4f8(%RSP,%RDX,1)

  (46) 0x4043de MOV	0x518(%RSP,%RDX,1),%RAX

  (46) 0x4043e6 ADD	$0x20,%RDX

  (46) 0x4043ea CMP	$0x700,%RDX

  (46) 0x4043f1 JNE	404390

0x4043f3 MOV	0xc08(%RSP),%RDX

0x4043fb VMOVDQU	0xc00(%RSP),%XMM1

0x404404 VPSRLQ	$0x1,%XMM1,%XMM2

0x404409 VPAND	%XMM2,%XMM13,%XMM2

0x40440d VEXTRACTI128	$0x1,%YMM0,%XMM0

0x404413 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

0x404419 VPSRLQ	$0x1,%XMM0,%XMM0

0x40441e VPAND	%XMM0,%XMM14,%XMM0

0x404422 VPTERNLOGQ	$0x56,0x1860(%RSP),%XMM2,%XMM0

0x40442e VPTESTMQ	%XMM15,%XMM1,%K1

0x404434 VPXORQ	%XMM16,%XMM0,%XMM0{%K1}

0x40443a VMOVDQU	%XMM0,0xbf8(%RSP)

0x404443 MOV	0xc10(%RSP),%RAX

0x40444b MOV	%EAX,%ESI

0x40444d SHR	$0x1,%ESI

0x40444f AND	$0x3fffffff,%ESI

0x404455 SHR	$0x1,%RDX

0x404458 AND	$-0x40000000,%RDX

0x40445f OR	%RSI,%RDX

0x404462 XOR	0x1870(%RSP),%RDX

0x40446a MOV	%EAX,%ESI

0x40446c AND	$0x1,%ESI

0x40446f NEG	%ESI

0x404471 AND	$-0x66f74f21,%ESI

0x404477 XOR	%RDX,%RSI

0x40447a MOV	%RSI,0xc08(%RSP)

0x404482 XOR	%EDX,%EDX

0x404484 NOPW	%CS:(%RAX,%RAX,1)

  (47) 0x404490 VMOVDQU	0xc18(%RSP,%RDX,1),%YMM0

  (47) 0x404499 VPSRLQ	$0x1,%YMM0,%YMM1

  (47) 0x40449e VPAND	%YMM3,%YMM1,%YMM1

  (47) 0x4044a2 VPBROADCASTQ	%RAX,%YMM2

  (47) 0x4044a8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

  (47) 0x4044ae VPSRLQ	$0x1,%YMM2,%YMM2

  (47) 0x4044b3 VPERMQ	$-0x6d,%YMM2,%YMM2

  (47) 0x4044b9 VPAND	%YMM4,%YMM2,%YMM2

  (47) 0x4044bd VPTERNLOGQ	$0x56,0x4f8(%RSP,%RDX,1),%YMM1,%YMM2

  (47) 0x4044c9 VPTESTMQ	%YMM5,%YMM0,%K1

  (47) 0x4044cf VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

  (47) 0x4044d5 VMOVDQU	%YMM2,0xc10(%RSP,%RDX,1)

  (47) 0x4044de MOV	0xc30(%RSP,%RDX,1),%RAX

  (47) 0x4044e6 ADD	$0x20,%RDX

  (47) 0x4044ea CMP	$0xc60,%RDX

  (47) 0x4044f1 JNE	404490

0x4044f3 MOV	0x1870(%RSP),%RDX

0x4044fb AND	%R9,%RDX

0x4044fe MOV	0x4f8(%RSP),%RAX

0x404506 MOV	%EAX,%ESI

0x404508 AND	$0x7ffffffe,%ESI

0x40450e OR	%RDX,%RSI

0x404511 SHR	$0x1,%RSI

0x404514 XOR	0x1158(%RSP),%RSI

0x40451c MOV	%EAX,%EDX

0x40451e AND	$0x1,%EDX

0x404521 NEG	%EDX

0x404523 AND	$-0x66f74f21,%EDX

0x404529 XOR	%RSI,%RDX

0x40452c MOV	%RDX,0x1870(%RSP)

0x404534 MOV	$0x1,%EDX

0x404539 MOV	%RAX,%RSI

0x40453c JMP	40433b

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.66
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	11.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.63
CQA cycles if no scalar integer	4.38
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.03
Front-end cycles	11.63
P0 cycles	8.04
P1 cycles	8.00
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	1.50
P5 cycles	7.96
P6 cycles	8.00
P7 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.50
Nb uops	46.50
Nb loads	4.50
Nb stores	1.50
Nb stack references	4.00
FLOP/cycle	0.09
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.90
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	11.11
Vectorization ratio load	33.33
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	10.00
Vector-efficiency ratio all	10.69
Vector-efficiency ratio load	16.67
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.43

Metric	Value
CQA speedup if no scalar integer	2.59
CQA speedup if FP arith vectorized	2.16
CQA speedup if fully vectorized	10.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.50
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	8.09
CQA cycles if fully vectorized	1.66
Front-end cycles	17.50
P0 cycles	11.83
P1 cycles	11.75
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	3.00
P5 cycles	11.67
P6 cycles	11.75
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	70.00
Nb loads	8.00
Nb stores	3.00
Nb stack references	8.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	22.22
Vectorization ratio load	66.67
Vectorization ratio store	33.33
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	20.83
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.03

Metric	Value
CQA speedup if no scalar integer	2.88
CQA speedup if FP arith vectorized	2.24
CQA speedup if fully vectorized	14.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.56
CQA cycles if fully vectorized	0.41
Front-end cycles	5.75
P0 cycles	4.25
P1 cycles	4.25
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.00
P5 cycles	4.25
P6 cycles	4.25
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.17
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.39
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.88
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.82

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl512

The loop is defined in /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558.

Analyzed code is defined in /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:407-409,412,420-423,458,462-466,3557-3558.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPTERNLOGQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 16 bytes (4 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	45.50
nb uops	46.50
loop length	206.50
used x86 registers	5
used mmx registers	0
used xmm registers	7
used ymm registers	0.50
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	11.63 cycles
front end	11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	8.04	8.00	2.25	2.25	1.50	7.96	8.00	1.50
cycles	8.04	8.00	2.25	2.25	1.50	7.96	8.00	1.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	11.63
Dispatch	8.04
Data deps.	0.00
Overall L1	11.63

Vectorization ratios

INT

all	11%
load	33%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	33%
store	33%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	10%
load	16%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	16%
store	16%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.63 cycles. At this rate:

2% of peak load performance is reached (2.98 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.50 to 6.75 cycles (2.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VPTERNLOGQ: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:408

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 80 bytes (20 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	68
nb uops	70
loop length	320
used x86 registers	6
used mmx registers	0
used xmm registers	10
used ymm registers	1
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	11.83	11.75	4.00	4.00	3.00	11.67	11.75	3.00
cycles	11.83	11.75	4.00	4.00	3.00	11.67	11.75	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	17.50
Dispatch	11.83
Data deps.	0.00
Overall L1	17.50

Vectorization ratios

INT

all	23%
load	66%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	22%
load	66%
store	33%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	12%
load	20%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	12%
load	20%
store	16%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.50 cycles. At this rate:

3% of peak load performance is reached (4.57 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.83 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.50 to 11.83 cycles (1.48x speedup).

ASM code

In the binary file, the address of the loop is: 404384

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x7,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%EDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %EDI,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VCVTUSI2SS %ESI,%XMM25,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS %XMM17,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS %XMM18,%XMM0	1	1	0	0	0	0	0	0	0	3	1	scal (6.3%)
JB 404550 <main+0x12a0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JB 404330 <main+0x1080>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc08(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVDQU 0xc00(%RSP),%XMM1	1	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPAND %XMM2,%XMM13,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPALIGNR $0x8,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VPAND %XMM0,%XMM14,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1860(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.50	0.50	0	0.33	0	0	1	0.50	vect (25.0%)
VPTESTMQ %XMM15,%XMM1,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPXORQ %XMM16,%XMM0,%XMM0{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xbf8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (25.0%)
MOV 0xc10(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $0x3fffffff,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
AND $-0x40000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
OR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR 0x1870(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND $-0x66f74f21,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xc08(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1870(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
AND %R9,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0x4f8(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1158(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND $-0x66f74f21,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0x1870(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
JMP 40433b <main+0x108b>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 2.00 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.41 cycles (14.15x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 8 bytes (2 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	23
loop length	93
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.25	4.25	0.50	0.50	0.00	4.25	4.25	0.00
cycles	4.25	4.25	0.50	0.50	0.00	4.25	4.25	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.75
Dispatch	4.25
Data deps.	0.00
Overall L1	5.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

1% of peak load performance is reached (1.39 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404384

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
MOV 0x4f8(%RSP,%RDX,8),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
INC %RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RDI	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %EDI,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0x7,%ESI	1	0.50	0	0	0	0	0.50	1	0.50	scal (6.3%)
AND $-0x62d3a980,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%EDI	1	0.50	0	0	0	0	0.50	1	0.50	scal (6.3%)
AND $-0x103a0000,%EDI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
XOR %RSI,%RDI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x12,%RSI	1	0.50	0	0	0	0	0.50	1	0.50	scal (12.5%)
XOR %EDI,%ESI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
VCVTUSI2SS %ESI,%XMM25,%XMM0	2	0.50	0.50	0	0	1	0	6	1	scal (6.3%)
VMULSS %XMM17,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS %XMM18,%XMM0	1	1	0	0	0	0	0	3	1	scal (6.3%)
JB 404550 <main+0x12a0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
CMP $0x270,%RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JB 404330 <main+0x1080>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks