OV - attention-icx-skl512 - Loop 41

	Loop Id: 41	Module: attention-icx-skl512	Source: random.tcc:404-3558 [...]	Coverage: 0.29%

0x4040a0 MOV	0xd0(%RSP),%RSI

0x4040a8 VMOVSS	%XMM0,(%RSI,%RCX,4)

0x4040ad INC	%RCX

0x4040b0 CMP	%R8,%RCX

0x4040b3 JE	4047b0

0x4040b9 VPBROADCASTQ	0xa22e(%RIP),%YMM3

0x4040c2 VPBROADCASTQ	0xa22d(%RIP),%YMM4

0x4040cb VPBROADCASTQ	0xa22c(%RIP),%YMM5

0x4040d4 VPBROADCASTQ	0xa22b(%RIP),%YMM6

0x4040dd JMP	404131

  (48) 0x4040e0 MOV	0x4f8(%RSP,%RDX,8),%RSI

  (48) 0x4040e8 INC	%RDX

  (48) 0x4040eb MOV	%RSI,%RDI

  (48) 0x4040ee SHR	$0xb,%RDI

  (48) 0x4040f2 MOV	%EDI,%EDI

  (48) 0x4040f4 XOR	%RSI,%RDI

  (48) 0x4040f7 MOV	%EDI,%ESI

  (48) 0x4040f9 SAL	$0x7,%ESI

  (48) 0x4040fc AND	$-0x62d3a980,%ESI

  (48) 0x404102 XOR	%RDI,%RSI

  (48) 0x404105 MOV	%ESI,%EDI

  (48) 0x404107 SAL	$0xf,%EDI

  (48) 0x40410a AND	$-0x103a0000,%EDI

  (48) 0x404110 XOR	%RSI,%RDI

  (48) 0x404113 MOV	%RDI,%RSI

  (48) 0x404116 SHR	$0x12,%RSI

  (48) 0x40411a XOR	%EDI,%ESI

  (48) 0x40411c VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (48) 0x404122 VMULSS	%XMM0,%XMM11,%XMM0

  (48) 0x404126 VUCOMISS	%XMM12,%XMM0

  (48) 0x40412b JB	404300

  (48) 0x404131 CMP	$0x270,%RDX

  (48) 0x404138 JB	4040e0

  (48) 0x40413a XOR	%EDX,%EDX

  (48) 0x40413c NOPL	(%RAX)

    (49) 0x404140 VMOVDQU	0x500(%RSP,%RDX,1),%YMM0

    (49) 0x404149 VPSRLQ	$0x1,%YMM0,%YMM1

    (49) 0x40414e VPAND	%YMM3,%YMM1,%YMM1

    (49) 0x404152 VPBROADCASTQ	%RAX,%YMM2

    (49) 0x404158 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (49) 0x40415e VPSRLQ	$0x1,%YMM2,%YMM2

    (49) 0x404163 VPERMQ	$-0x6d,%YMM2,%YMM2

    (49) 0x404169 VPAND	%YMM4,%YMM2,%YMM2

    (49) 0x40416d VPTERNLOGQ	$0x56,0x1160(%RSP,%RDX,1),%YMM1,%YMM2

    (49) 0x404179 VPTESTMQ	%YMM5,%YMM0,%K1

    (49) 0x40417f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (49) 0x404185 VMOVDQU	%YMM2,0x4f8(%RSP,%RDX,1)

    (49) 0x40418e MOV	0x518(%RSP,%RDX,1),%RAX

    (49) 0x404196 ADD	$0x20,%RDX

    (49) 0x40419a CMP	$0x700,%RDX

    (49) 0x4041a1 JNE	404140

  (48) 0x4041a3 MOV	0xc08(%RSP),%RDX

  (48) 0x4041ab VMOVDQU	0xc00(%RSP),%XMM1

  (48) 0x4041b4 VPSRLQ	$0x1,%XMM1,%XMM2

  (48) 0x4041b9 VPAND	%XMM7,%XMM2,%XMM2

  (48) 0x4041bd VEXTRACTI128	$0x1,%YMM0,%XMM0

  (48) 0x4041c3 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (48) 0x4041c9 VPSRLQ	$0x1,%XMM0,%XMM0

  (48) 0x4041ce VPAND	%XMM0,%XMM8,%XMM0

  (48) 0x4041d2 VPTERNLOGQ	$0x56,0x1860(%RSP),%XMM2,%XMM0

  (48) 0x4041de VPTESTMQ	%XMM9,%XMM1,%K1

  (48) 0x4041e4 VPXORQ	%XMM10,%XMM0,%XMM0{%K1}

  (48) 0x4041ea VMOVDQU	%XMM0,0xbf8(%RSP)

  (48) 0x4041f3 MOV	0xc10(%RSP),%RAX

  (48) 0x4041fb MOV	%EAX,%ESI

  (48) 0x4041fd SHR	$0x1,%ESI

  (48) 0x4041ff AND	$0x3fffffff,%ESI

  (48) 0x404205 SHR	$0x1,%RDX

  (48) 0x404208 AND	$-0x40000000,%RDX

  (48) 0x40420f OR	%RSI,%RDX

  (48) 0x404212 XOR	0x1870(%RSP),%RDX

  (48) 0x40421a MOV	%EAX,%ESI

  (48) 0x40421c AND	$0x1,%ESI

  (48) 0x40421f NEG	%ESI

  (48) 0x404221 AND	$-0x66f74f21,%ESI

  (48) 0x404227 XOR	%RDX,%RSI

  (48) 0x40422a MOV	%RSI,0xc08(%RSP)

  (48) 0x404232 XOR	%EDX,%EDX

  (48) 0x404234 NOPW	%CS:(%RAX,%RAX,1)

    (50) 0x404240 VMOVDQU	0xc18(%RSP,%RDX,1),%YMM0

    (50) 0x404249 VPSRLQ	$0x1,%YMM0,%YMM1

    (50) 0x40424e VPAND	%YMM3,%YMM1,%YMM1

    (50) 0x404252 VPBROADCASTQ	%RAX,%YMM2

    (50) 0x404258 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (50) 0x40425e VPSRLQ	$0x1,%YMM2,%YMM2

    (50) 0x404263 VPERMQ	$-0x6d,%YMM2,%YMM2

    (50) 0x404269 VPAND	%YMM4,%YMM2,%YMM2

    (50) 0x40426d VPTERNLOGQ	$0x56,0x4f8(%RSP,%RDX,1),%YMM1,%YMM2

    (50) 0x404279 VPTESTMQ	%YMM5,%YMM0,%K1

    (50) 0x40427f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (50) 0x404285 VMOVDQU	%YMM2,0xc10(%RSP,%RDX,1)

    (50) 0x40428e MOV	0xc30(%RSP,%RDX,1),%RAX

    (50) 0x404296 ADD	$0x20,%RDX

    (50) 0x40429a CMP	$0xc60,%RDX

    (50) 0x4042a1 JNE	404240

  (48) 0x4042a3 MOV	0x1870(%RSP),%RDX

  (48) 0x4042ab AND	%R9,%RDX

  (48) 0x4042ae MOV	0x4f8(%RSP),%RAX

  (48) 0x4042b6 MOV	%EAX,%ESI

  (48) 0x4042b8 AND	$0x7ffffffe,%ESI

  (48) 0x4042be OR	%RDX,%RSI

  (48) 0x4042c1 SHR	$0x1,%RSI

  (48) 0x4042c4 XOR	0x1158(%RSP),%RSI

  (48) 0x4042cc MOV	%EAX,%EDX

  (48) 0x4042ce AND	$0x1,%EDX

  (48) 0x4042d1 NEG	%EDX

  (48) 0x4042d3 AND	$-0x66f74f21,%EDX

  (48) 0x4042d9 XOR	%RSI,%RDX

  (48) 0x4042dc MOV	%RDX,0x1870(%RSP)

  (48) 0x4042e4 MOV	$0x1,%EDX

  (48) 0x4042e9 MOV	%RAX,%RSI

  (48) 0x4042ec JMP	4040eb

0x404300 VMOVSS	%XMM0,(%R13,%RCX,4)

0x404307 VPBROADCASTQ	0x9fe0(%RIP),%YMM3

0x404310 VPBROADCASTQ	0x9fdf(%RIP),%YMM4

0x404319 VPBROADCASTQ	0x9fde(%RIP),%YMM5

0x404322 VPBROADCASTQ	0x9fdd(%RIP),%YMM6

0x40432b JMP	404384

  (45) 0x404330 MOV	0x4f8(%RSP,%RDX,8),%RSI

  (45) 0x404338 INC	%RDX

  (45) 0x40433b MOV	%RSI,%RDI

  (45) 0x40433e SHR	$0xb,%RDI

  (45) 0x404342 MOV	%EDI,%EDI

  (45) 0x404344 XOR	%RSI,%RDI

  (45) 0x404347 MOV	%EDI,%ESI

  (45) 0x404349 SAL	$0x7,%ESI

  (45) 0x40434c AND	$-0x62d3a980,%ESI

  (45) 0x404352 XOR	%RDI,%RSI

  (45) 0x404355 MOV	%ESI,%EDI

  (45) 0x404357 SAL	$0xf,%EDI

  (45) 0x40435a AND	$-0x103a0000,%EDI

  (45) 0x404360 XOR	%RSI,%RDI

  (45) 0x404363 MOV	%RDI,%RSI

  (45) 0x404366 SHR	$0x12,%RSI

  (45) 0x40436a XOR	%EDI,%ESI

  (45) 0x40436c VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (45) 0x404372 VMULSS	%XMM17,%XMM0,%XMM0

  (45) 0x404378 VUCOMISS	%XMM18,%XMM0

  (45) 0x40437e JB	404550

  (45) 0x404384 CMP	$0x270,%RDX

  (45) 0x40438b JB	404330

  (45) 0x40438d XOR	%EDX,%EDX

  (45) 0x40438f NOP

    (46) 0x404390 VMOVDQU	0x500(%RSP,%RDX,1),%YMM0

    (46) 0x404399 VPSRLQ	$0x1,%YMM0,%YMM1

    (46) 0x40439e VPAND	%YMM3,%YMM1,%YMM1

    (46) 0x4043a2 VPBROADCASTQ	%RAX,%YMM2

    (46) 0x4043a8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (46) 0x4043ae VPSRLQ	$0x1,%YMM2,%YMM2

    (46) 0x4043b3 VPERMQ	$-0x6d,%YMM2,%YMM2

    (46) 0x4043b9 VPAND	%YMM4,%YMM2,%YMM2

    (46) 0x4043bd VPTERNLOGQ	$0x56,0x1160(%RSP,%RDX,1),%YMM1,%YMM2

    (46) 0x4043c9 VPTESTMQ	%YMM5,%YMM0,%K1

    (46) 0x4043cf VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (46) 0x4043d5 VMOVDQU	%YMM2,0x4f8(%RSP,%RDX,1)

    (46) 0x4043de MOV	0x518(%RSP,%RDX,1),%RAX

    (46) 0x4043e6 ADD	$0x20,%RDX

    (46) 0x4043ea CMP	$0x700,%RDX

    (46) 0x4043f1 JNE	404390

  (45) 0x4043f3 MOV	0xc08(%RSP),%RDX

  (45) 0x4043fb VMOVDQU	0xc00(%RSP),%XMM1

  (45) 0x404404 VPSRLQ	$0x1,%XMM1,%XMM2

  (45) 0x404409 VPAND	%XMM2,%XMM13,%XMM2

  (45) 0x40440d VEXTRACTI128	$0x1,%YMM0,%XMM0

  (45) 0x404413 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (45) 0x404419 VPSRLQ	$0x1,%XMM0,%XMM0

  (45) 0x40441e VPAND	%XMM0,%XMM14,%XMM0

  (45) 0x404422 VPTERNLOGQ	$0x56,0x1860(%RSP),%XMM2,%XMM0

  (45) 0x40442e VPTESTMQ	%XMM15,%XMM1,%K1

  (45) 0x404434 VPXORQ	%XMM16,%XMM0,%XMM0{%K1}

  (45) 0x40443a VMOVDQU	%XMM0,0xbf8(%RSP)

  (45) 0x404443 MOV	0xc10(%RSP),%RAX

  (45) 0x40444b MOV	%EAX,%ESI

  (45) 0x40444d SHR	$0x1,%ESI

  (45) 0x40444f AND	$0x3fffffff,%ESI

  (45) 0x404455 SHR	$0x1,%RDX

  (45) 0x404458 AND	$-0x40000000,%RDX

  (45) 0x40445f OR	%RSI,%RDX

  (45) 0x404462 XOR	0x1870(%RSP),%RDX

  (45) 0x40446a MOV	%EAX,%ESI

  (45) 0x40446c AND	$0x1,%ESI

  (45) 0x40446f NEG	%ESI

  (45) 0x404471 AND	$-0x66f74f21,%ESI

  (45) 0x404477 XOR	%RDX,%RSI

  (45) 0x40447a MOV	%RSI,0xc08(%RSP)

  (45) 0x404482 XOR	%EDX,%EDX

  (45) 0x404484 NOPW	%CS:(%RAX,%RAX,1)

    (47) 0x404490 VMOVDQU	0xc18(%RSP,%RDX,1),%YMM0

    (47) 0x404499 VPSRLQ	$0x1,%YMM0,%YMM1

    (47) 0x40449e VPAND	%YMM3,%YMM1,%YMM1

    (47) 0x4044a2 VPBROADCASTQ	%RAX,%YMM2

    (47) 0x4044a8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (47) 0x4044ae VPSRLQ	$0x1,%YMM2,%YMM2

    (47) 0x4044b3 VPERMQ	$-0x6d,%YMM2,%YMM2

    (47) 0x4044b9 VPAND	%YMM4,%YMM2,%YMM2

    (47) 0x4044bd VPTERNLOGQ	$0x56,0x4f8(%RSP,%RDX,1),%YMM1,%YMM2

    (47) 0x4044c9 VPTESTMQ	%YMM5,%YMM0,%K1

    (47) 0x4044cf VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (47) 0x4044d5 VMOVDQU	%YMM2,0xc10(%RSP,%RDX,1)

    (47) 0x4044de MOV	0xc30(%RSP,%RDX,1),%RAX

    (47) 0x4044e6 ADD	$0x20,%RDX

    (47) 0x4044ea CMP	$0xc60,%RDX

    (47) 0x4044f1 JNE	404490

  (45) 0x4044f3 MOV	0x1870(%RSP),%RDX

  (45) 0x4044fb AND	%R9,%RDX

  (45) 0x4044fe MOV	0x4f8(%RSP),%RAX

  (45) 0x404506 MOV	%EAX,%ESI

  (45) 0x404508 AND	$0x7ffffffe,%ESI

  (45) 0x40450e OR	%RDX,%RSI

  (45) 0x404511 SHR	$0x1,%RSI

  (45) 0x404514 XOR	0x1158(%RSP),%RSI

  (45) 0x40451c MOV	%EAX,%EDX

  (45) 0x40451e AND	$0x1,%EDX

  (45) 0x404521 NEG	%EDX

  (45) 0x404523 AND	$-0x66f74f21,%EDX

  (45) 0x404529 XOR	%RSI,%RDX

  (45) 0x40452c MOV	%RDX,0x1870(%RSP)

  (45) 0x404534 MOV	$0x1,%EDX

  (45) 0x404539 MOV	%RAX,%RSI

  (45) 0x40453c JMP	40433b

0x404550 MOV	0xd8(%RSP),%RSI

0x404558 VMOVSS	%XMM0,(%RSI,%RCX,4)

0x40455d VPBROADCASTQ	0x9d8a(%RIP),%YMM3

0x404566 VPBROADCASTQ	0x9d89(%RIP),%YMM4

0x40456f VPBROADCASTQ	0x9d88(%RIP),%YMM5

0x404578 VPBROADCASTQ	0x9d87(%RIP),%YMM6

0x404581 JMP	4045e4

  (42) 0x404590 MOV	0x4f8(%RSP,%RDX,8),%RSI

  (42) 0x404598 INC	%RDX

  (42) 0x40459b MOV	%RSI,%RDI

  (42) 0x40459e SHR	$0xb,%RDI

  (42) 0x4045a2 MOV	%EDI,%EDI

  (42) 0x4045a4 XOR	%RSI,%RDI

  (42) 0x4045a7 MOV	%EDI,%ESI

  (42) 0x4045a9 SAL	$0x7,%ESI

  (42) 0x4045ac AND	$-0x62d3a980,%ESI

  (42) 0x4045b2 XOR	%RDI,%RSI

  (42) 0x4045b5 MOV	%ESI,%EDI

  (42) 0x4045b7 SAL	$0xf,%EDI

  (42) 0x4045ba AND	$-0x103a0000,%EDI

  (42) 0x4045c0 XOR	%RSI,%RDI

  (42) 0x4045c3 MOV	%RDI,%RSI

  (42) 0x4045c6 SHR	$0x12,%RSI

  (42) 0x4045ca XOR	%EDI,%ESI

  (42) 0x4045cc VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (42) 0x4045d2 VMULSS	%XMM23,%XMM0,%XMM0

  (42) 0x4045d8 VUCOMISS	%XMM24,%XMM0

  (42) 0x4045de JB	4040a0

  (42) 0x4045e4 CMP	$0x270,%RDX

  (42) 0x4045eb JB	404590

  (42) 0x4045ed XOR	%EDX,%EDX

  (42) 0x4045ef NOP

    (43) 0x4045f0 VMOVDQU	0x500(%RSP,%RDX,1),%YMM0

    (43) 0x4045f9 VPSRLQ	$0x1,%YMM0,%YMM1

    (43) 0x4045fe VPAND	%YMM3,%YMM1,%YMM1

    (43) 0x404602 VPBROADCASTQ	%RAX,%YMM2

    (43) 0x404608 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (43) 0x40460e VPSRLQ	$0x1,%YMM2,%YMM2

    (43) 0x404613 VPERMQ	$-0x6d,%YMM2,%YMM2

    (43) 0x404619 VPAND	%YMM4,%YMM2,%YMM2

    (43) 0x40461d VPTERNLOGQ	$0x56,0x1160(%RSP,%RDX,1),%YMM1,%YMM2

    (43) 0x404629 VPTESTMQ	%YMM5,%YMM0,%K1

    (43) 0x40462f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (43) 0x404635 VMOVDQU	%YMM2,0x4f8(%RSP,%RDX,1)

    (43) 0x40463e MOV	0x518(%RSP,%RDX,1),%RAX

    (43) 0x404646 ADD	$0x20,%RDX

    (43) 0x40464a CMP	$0x700,%RDX

    (43) 0x404651 JNE	4045f0

  (42) 0x404653 MOV	0xc08(%RSP),%RDX

  (42) 0x40465b VMOVDQU	0xc00(%RSP),%XMM1

  (42) 0x404664 VPSRLQ	$0x1,%XMM1,%XMM2

  (42) 0x404669 VPANDQ	%XMM19,%XMM2,%XMM2

  (42) 0x40466f VEXTRACTI128	$0x1,%YMM0,%XMM0

  (42) 0x404675 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (42) 0x40467b VPSRLQ	$0x1,%XMM0,%XMM0

  (42) 0x404680 VPANDQ	%XMM20,%XMM0,%XMM0

  (42) 0x404686 VPTERNLOGQ	$0x56,0x1860(%RSP),%XMM2,%XMM0

  (42) 0x404692 VPTESTMQ	%XMM21,%XMM1,%K1

  (42) 0x404698 VPXORQ	%XMM22,%XMM0,%XMM0{%K1}

  (42) 0x40469e VMOVDQU	%XMM0,0xbf8(%RSP)

  (42) 0x4046a7 MOV	0xc10(%RSP),%RAX

  (42) 0x4046af MOV	%EAX,%ESI

  (42) 0x4046b1 SHR	$0x1,%ESI

  (42) 0x4046b3 AND	$0x3fffffff,%ESI

  (42) 0x4046b9 SHR	$0x1,%RDX

  (42) 0x4046bc AND	$-0x40000000,%RDX

  (42) 0x4046c3 OR	%RSI,%RDX

  (42) 0x4046c6 XOR	0x1870(%RSP),%RDX

  (42) 0x4046ce MOV	%EAX,%ESI

  (42) 0x4046d0 AND	$0x1,%ESI

  (42) 0x4046d3 NEG	%ESI

  (42) 0x4046d5 AND	$-0x66f74f21,%ESI

  (42) 0x4046db XOR	%RDX,%RSI

  (42) 0x4046de MOV	%RSI,0xc08(%RSP)

  (42) 0x4046e6 XOR	%EDX,%EDX

  (42) 0x4046e8 NOPL	(%RAX,%RAX,1)

    (44) 0x4046f0 VMOVDQU	0xc18(%RSP,%RDX,1),%YMM0

    (44) 0x4046f9 VPSRLQ	$0x1,%YMM0,%YMM1

    (44) 0x4046fe VPAND	%YMM3,%YMM1,%YMM1

    (44) 0x404702 VPBROADCASTQ	%RAX,%YMM2

    (44) 0x404708 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (44) 0x40470e VPSRLQ	$0x1,%YMM2,%YMM2

    (44) 0x404713 VPERMQ	$-0x6d,%YMM2,%YMM2

    (44) 0x404719 VPAND	%YMM4,%YMM2,%YMM2

    (44) 0x40471d VPTERNLOGQ	$0x56,0x4f8(%RSP,%RDX,1),%YMM1,%YMM2

    (44) 0x404729 VPTESTMQ	%YMM5,%YMM0,%K1

    (44) 0x40472f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (44) 0x404735 VMOVDQU	%YMM2,0xc10(%RSP,%RDX,1)

    (44) 0x40473e MOV	0xc30(%RSP,%RDX,1),%RAX

    (44) 0x404746 ADD	$0x20,%RDX

    (44) 0x40474a CMP	$0xc60,%RDX

    (44) 0x404751 JNE	4046f0

  (42) 0x404753 MOV	0x1870(%RSP),%RDX

  (42) 0x40475b AND	%R9,%RDX

  (42) 0x40475e MOV	0x4f8(%RSP),%RAX

  (42) 0x404766 MOV	%EAX,%ESI

  (42) 0x404768 AND	$0x7ffffffe,%ESI

  (42) 0x40476e OR	%RDX,%RSI

  (42) 0x404771 SHR	$0x1,%RSI

  (42) 0x404774 XOR	0x1158(%RSP),%RSI

  (42) 0x40477c MOV	%EAX,%EDX

  (42) 0x40477e AND	$0x1,%EDX

  (42) 0x404781 NEG	%EDX

  (42) 0x404783 AND	$-0x66f74f21,%EDX

  (42) 0x404789 XOR	%RSI,%RDX

  (42) 0x40478c MOV	%RDX,0x1870(%RSP)

  (42) 0x404794 MOV	$0x1,%EDX

  (42) 0x404799 MOV	%RAX,%RSI

  (42) 0x40479c JMP	40459b

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P2, P3,
Function	main
Source	random.tcc:422-422,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.81
Front-end cycles	5.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	14.00
Nb stores	3.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.71
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P2, P3,
Function	main
Source	random.tcc:422-422,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.81
Front-end cycles	5.75
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	14.00
Nb stores	3.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.71
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.75 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	23
nb uops	23
loop length	159
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	4
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	7.00	7.00	3.00	1.00	3.00	3.00
cycles	1.00	1.00	7.00	7.00	3.00	1.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	7.00
Overall L1	7.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

12% of peak load performance is reached (16.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4040b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xd0(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4047b0 <main+0x1500>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0xa22e(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22d(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22c(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22b(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404131 <main+0xe81>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%R13,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9fe0(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fdf(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fde(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fdd(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404384 <main+0x10d4>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0xd8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9d8a(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d89(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d88(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d87(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 4045e4 <main+0x1334>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.75 cycles (1.22x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	23
nb uops	23
loop length	159
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	4
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	7.00	7.00	3.00	1.00	3.00	3.00
cycles	1.00	1.00	7.00	7.00	3.00	1.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	7.00
Overall L1	7.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

12% of peak load performance is reached (16.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4040b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xd0(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4047b0 <main+0x1500>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0xa22e(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22d(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22c(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa22b(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404131 <main+0xe81>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%R13,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9fe0(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fdf(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fde(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9fdd(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404384 <main+0x10d4>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0xd8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9d8a(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d89(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d88(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d87(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 4045e4 <main+0x1334>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code