OV - attention-icx-skl512 - Loop 38

0x404820 LEA	0x1(%RCX),%EDX

0x404823 MOV	0xb8(%RSP),%RSI

0x40482b ADD	%RSI,%RAX

0x40482e CMP	0xac(%RSP),%ECX

0x404835 MOV	%EDX,%ECX

0x404837 JE	404a00

0x40483d MOV	%ECX,%EDX

0x40483f IMUL	%ESI,%EDX

0x404842 VPBROADCASTD	%EDX,%YMM0

0x404848 XOR	%ESI,%ESI

0x40484a JMP	40492d

  (39) 0x404850 VPXOR	%XMM2,%XMM2,%XMM2

  (39) 0x404854 XOR	%EDI,%EDI

  (39) 0x404856 VPBROADCASTQ	%RDI,%ZMM3

  (39) 0x40485c VMOVDQU64	0x340(%RSP),%ZMM4

  (39) 0x404864 VPSUBQ	%ZMM3,%ZMM4,%ZMM4

  (39) 0x40486a VPCMPGTQ	%ZMM12,%ZMM4,%K1

  (39) 0x404870 VPMOVQD	%ZMM3,%YMM3

  (39) 0x404876 VPADDD	%YMM3,%YMM13,%YMM3

  (39) 0x40487a VPADDD	%YMM3,%YMM0,%YMM4

  (39) 0x40487e LEA	(%RBX,%R14,1),%RDI

  (39) 0x404882 VPBROADCASTD	0x9779(%RIP),%YMM6

  (39) 0x40488b VPSUBD	%YMM6,%YMM4,%YMM4

  (39) 0x40488f VXORPS	%XMM5,%XMM5,%XMM5

  (39) 0x404893 KMOVQ	%K1,%K2

  (39) 0x404898 VGATHERDPS	(%RDI,%YMM4,4),%YMM5{%K2}

  (39) 0x40489f VMOVAPS	%YMM5,%YMM11{%K1}

  (39) 0x4048a5 VCVTPS2PD	%YMM11,%ZMM4

  (39) 0x4048ab VPMULLD	0x1c0(%RSP),%YMM3,%YMM3

  (39) 0x4048b5 VPADDD	%YMM3,%YMM1,%YMM1

  (39) 0x4048b9 LEA	(%R13,%R14,1),%RDI

  (39) 0x4048be VPSUBD	%YMM6,%YMM1,%YMM1

  (39) 0x4048c2 VPXOR	%XMM3,%XMM3,%XMM3

  (39) 0x4048c6 KMOVQ	%K1,%K2

  (39) 0x4048cb VGATHERDPS	(%RDI,%YMM1,4),%YMM3{%K2}

  (39) 0x4048d2 VMOVAPS	%YMM3,%YMM10{%K1}

  (39) 0x4048d8 VCVTPS2PD	%YMM10,%ZMM1

  (39) 0x4048de VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

  (39) 0x4048e4 VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

  (39) 0x4048eb VADDPD	%ZMM3,%ZMM1,%ZMM1

  (39) 0x4048f1 VEXTRACTF128	$0x1,%YMM1,%XMM3

  (39) 0x4048f7 VADDPD	%XMM3,%XMM1,%XMM1

  (39) 0x4048fb VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

  (39) 0x404900 VADDSD	%XMM3,%XMM1,%XMM1

  (39) 0x404904 VADDSD	%XMM1,%XMM2,%XMM2

  (39) 0x404908 VCVTSD2SS	%XMM2,%XMM2,%XMM1

  (39) 0x40490c LEA	(%RDX,%RSI,1),%EDI

  (39) 0x40490f MOV	0xc8(%RSP),%R8

  (39) 0x404917 VMOVSS	%XMM1,(%R8,%RDI,4)

  (39) 0x40491d LEA	0x1(%RSI),%RDI

  (39) 0x404921 CMP	%R10,%RSI

  (39) 0x404924 MOV	%RDI,%RSI

  (39) 0x404927 JE	404820

  (39) 0x40492d VPBROADCASTD	%ESI,%YMM1

  (39) 0x404933 TEST	%R15,%R15

  (39) 0x404936 JE	404850

  (39) 0x40493c VPXOR	%XMM2,%XMM2,%XMM2

  (39) 0x404940 XOR	%EDI,%EDI

  (39) 0x404942 VMOVDQU	0x1c0(%RSP),%YMM6

  (39) 0x40494b NOPL	(%RAX,%RAX,1)

    (40) 0x404950 LEA	(%RAX,%RDI,1),%R8D

    (40) 0x404954 VPBROADCASTD	%R8D,%YMM3

    (40) 0x40495a LEA	(%RBX,%R14,1),%R8

    (40) 0x40495e VPCMPEQB	%XMM0,%XMM0,%K1

    (40) 0x404964 VPXOR	%XMM4,%XMM4,%XMM4

    (40) 0x404968 VPBROADCASTD	%EDI,%YMM5

    (40) 0x40496e VPADDD	%YMM3,%YMM9,%YMM3

    (40) 0x404972 VPADDD	%YMM7,%YMM5,%YMM5

    (40) 0x404976 VPMULLD	%YMM5,%YMM6,%YMM5

    (40) 0x40497b VPADDD	%YMM5,%YMM1,%YMM5

    (40) 0x40497f LEA	(%R13,%R14,1),%R9

    (40) 0x404984 VPSUBD	%YMM8,%YMM5,%YMM5

    (40) 0x404989 VPCMPEQB	%XMM0,%XMM0,%K2

    (40) 0x40498f VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}

    (40) 0x404996 VXORPS	%XMM3,%XMM3,%XMM3

    (40) 0x40499a VGATHERDPS	(%R9,%YMM5,4),%YMM3{%K2}

    (40) 0x4049a1 VCVTPS2PD	%YMM4,%ZMM4

    (40) 0x4049a7 VCVTPS2PD	%YMM3,%ZMM3

    (40) 0x4049ad VFMADD231PD	%ZMM3,%ZMM4,%ZMM2

    (40) 0x4049b3 ADD	$0x8,%RDI

    (40) 0x4049b7 CMP	%R15,%RDI

    (40) 0x4049ba JB	404950

  (39) 0x4049bc VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

  (39) 0x4049c3 VADDPD	%ZMM3,%ZMM2,%ZMM2

  (39) 0x4049c9 VEXTRACTF128	$0x1,%YMM2,%XMM3

  (39) 0x4049cf VADDPD	%XMM3,%XMM2,%XMM2

  (39) 0x4049d3 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (39) 0x4049d8 VADDSD	%XMM3,%XMM2,%XMM2

  (39) 0x4049dc MOV	%R15,%RDI

  (39) 0x4049df TESTB	$0x1,0x110(%RSP)

  (39) 0x4049e7 JE	404856

  (39) 0x4049ed JMP	404908

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 98

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-31
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.20
Front-end cycles	2.75
P0 cycles	1.75
P1 cycles	2.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.00
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	2.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-31
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.20
Front-end cycles	2.75
P0 cycles	1.75
P1 cycles	2.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.00
P5 cycles	1.75
P6 cycles	1.75
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 1.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	11
nb uops	11
loop length	47
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.75	1.75	1.00	1.00	0.00	1.75	1.75	0.00
cycles	1.75	2.00	1.00	1.00	0.00	1.75	1.75	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.75
Dispatch	2.00
Data deps.	0.00
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

3% of peak load performance is reached (4.36 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 40483d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%EDX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0xb8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%ECX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
JE 404a00 <main+0x1750>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %ESI,%EDX	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %EDX,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 40492d <main+0x167d>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.75 to 1.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	11
nb uops	11
loop length	47
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.75 cycles
front end	2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.75	1.75	1.00	1.00	0.00	1.75	1.75	0.00
cycles	1.75	2.00	1.00	1.00	0.00	1.75	1.75	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.75
Dispatch	2.00
Data deps.	0.00
Overall L1	2.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

3% of peak load performance is reached (4.36 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.75 to 2.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the loop is: 40483d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%EDX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0xb8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%ECX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
JE 404a00 <main+0x1750>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %ESI,%EDX	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %EDX,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 40492d <main+0x167d>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code