OV - attention-icx-skl512 - Loop 33

	Loop Id: 33	Module: attention-icx-skl512	Source: attention_v2.cpp:27-98 [...]	Coverage: 2.75%

0x404d90 VXORPD	%XMM2,%XMM2,%XMM2

0x404d94 XOR	%EDI,%EDI

0x404d96 VPBROADCASTQ	%RDI,%ZMM3

0x404d9c VMOVDQU64	0x340(%RSP),%ZMM4

0x404da4 VPSUBQ	%ZMM3,%ZMM4,%ZMM4

0x404daa VPCMPGTQ	%ZMM13,%ZMM4,%K1

0x404db0 VPMOVQD	%ZMM3,%YMM3

0x404db6 VPADDD	%YMM3,%YMM14,%YMM3

0x404dba VPADDD	%YMM3,%YMM0,%YMM4

0x404dbe LEA	(%RBX,%R14,1),%RDI

0x404dc2 VPBROADCASTD	0x9239(%RIP),%YMM6

0x404dcb VPSUBD	%YMM6,%YMM4,%YMM4

0x404dcf VXORPS	%XMM5,%XMM5,%XMM5

0x404dd3 KMOVQ	%K1,%K2

0x404dd8 VGATHERDPS	(%RDI,%YMM4,4),%YMM5{%K2}

0x404ddf VMOVAPS	%YMM5,%YMM12{%K1}

0x404de5 VCVTPS2PD	%YMM12,%ZMM4

0x404deb VPMULLD	0x1c0(%RSP),%YMM3,%YMM3

0x404df5 VPADDD	%YMM3,%YMM1,%YMM1

0x404df9 MOV	0xd0(%RSP),%RDI

0x404e01 LEA	(%RDI,%R14,1),%RDI

0x404e05 VPSUBD	%YMM6,%YMM1,%YMM1

0x404e09 VPXOR	%XMM3,%XMM3,%XMM3

0x404e0d KMOVQ	%K1,%K2

0x404e12 VGATHERDPS	(%RDI,%YMM1,4),%YMM3{%K2}

0x404e19 VMOVAPS	%YMM3,%YMM11{%K1}

0x404e1f VCVTPS2PD	%YMM11,%ZMM1

0x404e25 VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

0x404e2b VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

0x404e32 VADDPD	%ZMM3,%ZMM1,%ZMM1

0x404e38 VEXTRACTF128	$0x1,%YMM1,%XMM3

0x404e3e VADDPD	%XMM3,%XMM1,%XMM1

0x404e42 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

0x404e47 VADDSD	%XMM3,%XMM1,%XMM1

0x404e4b VADDSD	%XMM1,%XMM2,%XMM2

0x404e4f VCVTSD2SS	%XMM2,%XMM2,%XMM1

0x404e53 LEA	(%RDX,%RSI,1),%EDI

0x404e56 MOV	0xe8(%RSP),%R8

0x404e5e VMOVSS	%XMM1,(%R8,%RDI,4)

0x404e64 LEA	0x1(%RSI),%RDI

0x404e68 CMP	%R11,%RSI

0x404e6b MOV	%RDI,%RSI

0x404e6e JE	404d60

0x404e74 VPBROADCASTD	%ESI,%YMM1

0x404e7a TEST	%R15,%R15

0x404e7d JE	404d90

0x404e83 VXORPD	%XMM2,%XMM2,%XMM2

0x404e87 XOR	%EDI,%EDI

0x404e89 NOPL	(%RAX)

  (34) 0x404e90 LEA	(%RAX,%RDI,1),%R8D

  (34) 0x404e94 VPBROADCASTD	%R8D,%YMM3

  (34) 0x404e9a LEA	(%RBX,%R14,1),%R8

  (34) 0x404e9e VXORPD	%XMM4,%XMM4,%XMM4

  (34) 0x404ea2 VPCMPEQB	%XMM0,%XMM0,%K1

  (34) 0x404ea8 VPBROADCASTD	%EDI,%YMM5

  (34) 0x404eae VPADDD	%YMM3,%YMM10,%YMM3

  (34) 0x404eb2 VPADDD	%YMM5,%YMM8,%YMM5

  (34) 0x404eb6 VPMULLD	%YMM5,%YMM7,%YMM5

  (34) 0x404ebb VPADDD	%YMM5,%YMM1,%YMM5

  (34) 0x404ebf LEA	(%R10,%R14,1),%R9

  (34) 0x404ec3 VPSUBD	%YMM9,%YMM5,%YMM5

  (34) 0x404ec8 VXORPS	%XMM6,%XMM6,%XMM6

  (34) 0x404ecc VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}

  (34) 0x404ed3 VPCMPEQB	%XMM0,%XMM0,%K1

  (34) 0x404ed9 VGATHERDPS	(%R9,%YMM5,4),%YMM6{%K1}

  (34) 0x404ee0 VCVTPS2PD	%YMM4,%ZMM3

  (34) 0x404ee6 VCVTPS2PD	%YMM6,%ZMM4

  (34) 0x404eec VFMADD231PD	%ZMM4,%ZMM3,%ZMM2

  (34) 0x404ef2 ADD	$0x8,%RDI

  (34) 0x404ef6 CMP	%R15,%RDI

  (34) 0x404ef9 JB	404e90

0x404efb VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

0x404f02 VADDPD	%ZMM3,%ZMM2,%ZMM2

0x404f08 VEXTRACTF128	$0x1,%YMM2,%XMM3

0x404f0e VADDPD	%XMM3,%XMM2,%XMM2

0x404f12 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x404f17 VADDSD	%XMM3,%XMM2,%XMM2

0x404f1b MOV	%R15,%RDI

0x404f1e TESTB	$0x1,0x110(%RSP)

0x404f26 JE	404d96

0x404f2c JMP	404e4f

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 98

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.16
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.16
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.33
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	11.53
CQA cycles if fully vectorized	8.17
Front-end cycles	12.33
P0 cycles	10.06
P1 cycles	9.86
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	1.00
P5 cycles	10.67
P6 cycles	4.42
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	49.33
Nb loads	5.67
Nb stores	1.00
Nb stack references	3.67
FLOP/cycle	1.68
Nb FLOP add-sub	15.33
Nb FLOP mul	5.33
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.76
Bytes prefetched	0.00
Bytes loaded	123.33
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	66.92
Vectorization ratio load	80.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	74.53
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	65.87
Vector-efficiency ratio all	38.07
Vector-efficiency ratio load	51.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	48.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.89

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	1.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	13.24
CQA cycles if fully vectorized	9.45
Front-end cycles	14.00
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	10.50
P3 cycles	10.50
P4 cycles	1.00
P5 cycles	12.00
P6 cycles	3.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	56.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	1.43
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.14
Bytes prefetched	0.00
Bytes loaded	180.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.76
Vectorization ratio load	80.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	73.68
Vector-efficiency ratio all	44.89
Vector-efficiency ratio load	51.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	38.16

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	4.13
Front-end cycles	6.25
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	4.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	25.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	1.76
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.08
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	50.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	26.04
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.09

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.52
CQA cycles if fully vectorized	10.94
Front-end cycles	16.75
P0 cycles	13.67
P1 cycles	13.33
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	1.00
P5 cycles	15.00
P6 cycles	6.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	67.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	1.85
Nb FLOP add-sub	23.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.04
Bytes prefetched	0.00
Bytes loaded	181.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	75.00
Vectorization ratio load	80.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	73.91
Vector-efficiency ratio all	43.28
Vector-efficiency ratio load	51.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	49.04
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	36.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30-33,98.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.33 to 8.17 cycles (1.51x speedup).

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
74% of SSE/AVX addition or subtraction instructions are used in vector version.
65% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VGATHERDPS: 0 occurrences
VPMULLD: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences
VPMOVQD: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20.666666666667 FP arithmetical operations:

15.33: addition or subtraction
5.33: multiply

The binary loop is loading 123 bytes (15 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	42
nb uops	49.33
loop length	220.33
used x86 registers	9
used mmx registers	0
used xmm registers	3.67
used ymm registers	7.33
used zmm registers	3.67
nb stack references	3.67
ADD-SUB / MUL ratio	5.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	12.33 cycles
front end	12.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	10.06	9.86	7.50	7.50	1.00	10.67	4.42	1.00
cycles	10.06	9.86	7.50	7.50	1.00	10.67	4.42	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.33
Dispatch	10.67
Data deps.	0.00
Overall L1	12.33

Vectorization ratios

INT

all	47%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	74%
load	100%
store	0%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

INT+FP

all	66%
load	80%
store	0%
mul	100%
add-sub	74%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	65%

Vector efficiency ratios

INT

all	36%
load	52%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	37%
load	50%
store	6%
mul	100%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

INT+FP

all	38%
load	51%
store	6%
mul	75%
add-sub	48%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.33 cycles. At this rate:

6% of peak load performance is reached (8.37 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.39 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 12.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.00 to 9.45 cycles (1.48x speedup).

Details

75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
80% of SSE/AVX addition or subtraction instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.02x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction
8: multiply

The binary loop is loading 180 bytes (22 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	46
nb uops	56
loop length	243
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	4
nb stack references	4
ADD-SUB / MUL ratio	4.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.00	12.00	10.50	10.50	1.00	12.00	3.00	1.00
cycles	12.00	12.00	10.50	10.50	1.00	12.00	3.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	14.00
Dispatch	12.00
Data deps.	0.00
Overall L1	14.00

Vectorization ratios

INT

all	73%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	77%
load	100%
store	0%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	91%

INT+FP

all	75%
load	80%
store	0%
mul	100%
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	50%
load	52%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	39%
load	50%
store	6%
mul	100%
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	44%
load	51%
store	6%
mul	75%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

10% of peak load performance is reached (12.86 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 12.00 cycles (1.17x speedup).

ASM code

In the binary file, the address of the loop is: 404e74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTQ %RDI,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQU64 0x340(%RSP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPCMPGTQ %ZMM13,%ZMM4,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM14,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
LEA (%RBX,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPBROADCASTD 0x9239(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM12,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x1c0(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xd0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RDI,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xe8(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404d60 <main+0x1ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 404d90 <main+0x1ae0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.25 to 5.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.25 to 4.13 cycles (1.51x speedup).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

11: addition or subtraction

The binary loop is loading 9 bytes (1 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.85 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	25
loop length	119
used x86 registers	8
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	2
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.50	4.25	1.00	1.00	1.00	5.00	4.25	1.00
cycles	4.50	4.25	1.00	1.00	1.00	5.00	4.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.25
Dispatch	5.00
Data deps.	0.00
Overall L1	6.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

1% of peak load performance is reached (1.44 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404e74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xe8(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404d60 <main+0x1ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 404d90 <main+0x1ae0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TESTB $0x1,0x110(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 404d96 <main+0x1ae6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 404e4f <main+0x1b9f>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.75 to 15.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.75 to 10.94 cycles (1.53x speedup).

Details

75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.02x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

23: addition or subtraction
8: multiply

The binary loop is loading 181 bytes (22 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	67
loop length	299
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	5
nb stack references	5
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.75 cycles
front end	16.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	13.67	13.33	11.00	11.00	1.00	15.00	6.00	1.00
cycles	13.67	13.33	11.00	11.00	1.00	15.00	6.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	16.75
Dispatch	15.00
Data deps.	0.00
Overall L1	16.75

Vectorization ratios

INT

all	68%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	79%
load	100%
store	0%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

INT+FP

all	75%
load	80%
store	0%
mul	100%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	48%
load	52%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	39%
load	50%
store	6%
mul	100%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

INT+FP

all	43%
load	51%
store	6%
mul	75%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.75 cycles. At this rate:

8% of peak load performance is reached (10.81 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404e74

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDI,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQU64 0x340(%RSP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPCMPGTQ %ZMM13,%ZMM4,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM14,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
LEA (%RBX,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPBROADCASTD 0x9239(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM12,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x1c0(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xd0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RDI,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xe8(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R11,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404d60 <main+0x1ab0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 404d90 <main+0x1ae0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TESTB $0x1,0x110(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 404d96 <main+0x1ae6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop