OV - attention-icx-skl512 - Loop 29

0x404fb0 MOV	0x128(%RSP),%RCX

0x404fb8 LEA	0x1(%RCX),%RSI

0x404fbc MOV	0x80(%RSP),%RAX

0x404fc4 ADD	0xb8(%RSP),%EAX

0x404fcb CMP	0x188(%RSP),%RCX

0x404fd3 JE	405150

0x404fd9 MOV	%RAX,0x80(%RSP)

0x404fe1 MOV	%EAX,%EAX

0x404fe3 MOV	%RAX,0x100(%RSP)

0x404feb MOV	%RSI,0x128(%RSP)

0x404ff3 LEA	(%R12,%RSI,4),%RSI

0x404ff7 CMPL	$0x8,0x148(%RSP)

0x404fff MOV	0x120(%RSP),%RAX

0x405007 MOV	0x198(%RSP),%ECX

0x40500e MOV	0x240(%RSP),%RDI

0x405016 MOV	0x238(%RSP),%RDX

0x40501e JB	4050fc

0x405024 MOV	0x118(%RSP),%R8

0x40502c MOV	0x100(%RSP),%R9

0x405034 LEA	(%R8,%R9,4),%R8

0x405038 XOR	%R9D,%R9D

0x40503b XOR	%R10D,%R10D

0x40503e XCHG	%AX,%AX

  (31) 0x405040 MOV	%R9D,%R11D

  (31) 0x405043 VMOVSS	-0x1c(%R8,%R10,1),%XMM0

  (31) 0x40504a VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x405050 LEA	(%RAX,%R9,1),%R11D

  (31) 0x405054 VMOVSS	-0x18(%R8,%R10,1),%XMM0

  (31) 0x40505b VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x405061 MOV	0x270(%RSP),%R11

  (31) 0x405069 ADD	%R9D,%R11D

  (31) 0x40506c VMOVSS	-0x14(%R8,%R10,1),%XMM0

  (31) 0x405073 VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x405079 MOV	0x268(%RSP),%R11

  (31) 0x405081 LEA	(%R11,%R9,1),%R11D

  (31) 0x405085 VMOVSS	-0x10(%R8,%R10,1),%XMM0

  (31) 0x40508c VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x405092 MOV	0x260(%RSP),%R11

  (31) 0x40509a LEA	(%R11,%R9,1),%R11D

  (31) 0x40509e VMOVSS	-0xc(%R8,%R10,1),%XMM0

  (31) 0x4050a5 VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x4050ab MOV	0x258(%RSP),%R11

  (31) 0x4050b3 LEA	(%R11,%R9,1),%R11D

  (31) 0x4050b7 VMOVSS	-0x8(%R8,%R10,1),%XMM0

  (31) 0x4050be VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x4050c4 LEA	(%RDX,%R9,1),%R11D

  (31) 0x4050c8 VMOVSS	-0x4(%R8,%R10,1),%XMM0

  (31) 0x4050cf VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x4050d5 VMOVSS	(%R8,%R10,1),%XMM0

  (31) 0x4050db MOV	0x278(%RSP),%R11

  (31) 0x4050e3 ADD	%R9D,%R11D

  (31) 0x4050e6 VMOVSS	%XMM0,(%RSI,%R11,4)

  (31) 0x4050ec ADD	$0x20,%R10

  (31) 0x4050f0 ADD	%ECX,%R9D

  (31) 0x4050f3 CMP	%R10,%RDI

  (31) 0x4050f6 JNE	405040

0x4050fc MOV	0x148(%RSP),%R11

0x405104 CMP	%R11,%R15

0x405107 JAE	404fb0

0x40510d MOV	0xc0(%RSP),%RCX

0x405115 MOV	0x100(%RSP),%RDX

0x40511d LEA	(%RCX,%RDX,4),%RDI

0x405121 MOV	0x228(%RSP),%R8

0x405129 MOV	%R15,%R9

0x40512c NOPL	(%RAX)

  (30) 0x405130 VMOVSS	(%RDI,%R9,4),%XMM0

  (30) 0x405136 MOV	%R8D,%R10D

  (30) 0x405139 VMOVSS	%XMM0,(%RSI,%R10,4)

  (30) 0x40513f INC	%R9

  (30) 0x405142 ADD	%RAX,%R8

  (30) 0x405145 CMP	%R9,%R11

  (30) 0x405148 JNE	405130

0x40514a JMP	404fb0

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h: 1254 - 1254

--------------------------------------------------------------------------------

1254: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 233 - 238

--------------------------------------------------------------------------------

233:       start = std::chrono::steady_clock::now();

234: #endif

235:

236:       for (int i = 0; i < context_size; ++i)

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.56
CQA cycles if no scalar integer	6.56
CQA cycles if FP arith vectorized	6.56
CQA cycles if fully vectorized	0.53
Front-end cycles	6.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.50
Nb uops	26.00
Nb loads	12.50
Nb stores	3.00
Nb stack references	11.50
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.22
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	0.67
Stride 1	0.67
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.91
Vector-efficiency ratio load	10.70
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.72

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	8.25
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	0.59
Front-end cycles	8.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	15.00
Nb stores	3.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.71
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	0.53
Front-end cycles	6.25
P0 cycles	2.25
P1 cycles	2.25
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	3.00
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	12.00
Nb stores	3.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.28
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	7.81

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	0.52
Front-end cycles	6.75
P0 cycles	2.75
P1 cycles	2.75
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	3.00
P5 cycles	2.75
P6 cycles	2.75
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	13.00
Nb stores	3.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.19
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.47
Front-end cycles	4.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	3.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	19.00
Nb loads	10.00
Nb stores	3.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.40
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.80
Vector-efficiency ratio load	10.71
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.56 to 0.53 cycles (12.44x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26.50
nb uops	26
loop length	167
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	6.25	6.25	3.00	2.50	2.50	3.00
cycles	2.50	2.50	6.25	6.25	3.00	2.50	2.50	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.50
Dispatch	6.25
Data deps.	0.00
Overall L1	6.56

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.56 cycles. At this rate:

10% of peak load performance is reached (13.44 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.78 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 0.59 cycles (13.89x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	33
nb uops	33
loop length	201
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	7.50	7.50	3.00	3.00	3.00	3.00
cycles	3.00	3.00	7.50	7.50	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.25
Dispatch	7.50
Data deps.	0.00
Overall L1	8.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

10% of peak load performance is reached (13.09 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 404fd9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD 0xb8(%RSP),%EAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
CMP 0x188(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 405150 <main+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x128(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%R12,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x8,0x148(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x198(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x240(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x238(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JB 4050fc <main+0x1e4c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x118(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x100(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R8,%R9,4),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x148(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP %R11,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JAE 404fb0 <main+0x1d00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x100(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RCX,%RDX,4),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x228(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404fb0 <main+0x1d00>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.25 to 0.53 cycles (11.76x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 84 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26
nb uops	25
loop length	161
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.25	2.25	6.00	6.00	3.00	2.25	2.25	3.00
cycles	2.25	2.25	6.00	6.00	3.00	2.25	2.25	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.25
Dispatch	6.00
Data deps.	0.00
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

10% of peak load performance is reached (13.44 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 404fd9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD 0xb8(%RSP),%EAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
CMP 0x188(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 405150 <main+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RAX,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x128(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%R12,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x8,0x148(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x198(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x240(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x238(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JB 4050fc <main+0x1e4c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x118(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x100(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R8,%R9,4),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x148(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP %R11,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JAE 404fb0 <main+0x1d00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 0.52 cycles (13.09x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 92 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	27
loop length	173
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.75	2.75	6.50	6.50	3.00	2.75	2.75	3.00
cycles	2.75	2.75	6.50	6.50	3.00	2.75	2.75	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.75
Dispatch	6.50
Data deps.	0.00
Overall L1	6.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

10% of peak load performance is reached (13.63 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 404fd9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD 0xb8(%RSP),%EAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
CMP 0x188(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 405150 <main+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x128(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%R12,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x8,0x148(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x198(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x240(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x238(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JB 4050fc <main+0x1e4c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x148(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP %R11,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JAE 404fb0 <main+0x1d00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x100(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RCX,%RDX,4),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x228(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404fb0 <main+0x1d00>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.47 cycles (10.67x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.75 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	20
nb uops	19
loop length	133
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	5.00	5.00	3.00	2.00	2.00	3.00
cycles	2.00	2.00	5.00	5.00	3.00	2.00	2.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	5.00
Data deps.	0.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

10% of peak load performance is reached (13.60 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404fd9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x128(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x80(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
ADD 0xb8(%RSP),%EAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
CMP 0x188(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 405150 <main+0x1ea0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RAX,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RSI,0x128(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%R12,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMPL $0x8,0x148(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x198(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x240(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x238(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JB 4050fc <main+0x1e4c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x148(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
CMP %R11,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JAE 404fb0 <main+0x1d00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end