OV - attention-icx-skl512 - Loop 27

	Loop Id: 27	Module: attention-icx-skl512	Source: attention_v2.cpp:27-98 [...]	Coverage: 11.85%

0x405240 VXORPD	%XMM2,%XMM2,%XMM2

0x405244 XOR	%R8D,%R8D

0x405247 VPBROADCASTQ	%R8,%ZMM3

0x40524d VMOVDQU64	0x340(%RSP),%ZMM4

0x405255 VPSUBQ	%ZMM3,%ZMM4,%ZMM4

0x40525b VPCMPGTQ	%ZMM13,%ZMM4,%K1

0x405261 VPMOVQD	%ZMM3,%YMM3

0x405267 VPADDD	%YMM3,%YMM14,%YMM3

0x40526b VPADDD	%YMM3,%YMM0,%YMM4

0x40526f MOV	0xc8(%RSP),%R8

0x405277 ADD	%R14,%R8

0x40527a VPBROADCASTD	0x8d81(%RIP),%YMM6

0x405283 VPSUBD	%YMM6,%YMM4,%YMM4

0x405287 VXORPS	%XMM5,%XMM5,%XMM5

0x40528b KMOVQ	%K1,%K2

0x405290 VGATHERDPS	(%R8,%YMM4,4),%YMM5{%K2}

0x405297 VMOVAPS	%YMM5,%YMM12{%K1}

0x40529d VCVTPS2PD	%YMM12,%ZMM4

0x4052a3 VPMULLD	0x320(%RSP),%YMM3,%YMM3

0x4052ad VPADDD	%YMM3,%YMM1,%YMM1

0x4052b1 LEA	(%R12,%R14,1),%R8

0x4052b5 VPSUBD	%YMM6,%YMM1,%YMM1

0x4052b9 VPXOR	%XMM3,%XMM3,%XMM3

0x4052bd KMOVQ	%K1,%K2

0x4052c2 VGATHERDPS	(%R8,%YMM1,4),%YMM3{%K2}

0x4052c9 VMOVAPS	%YMM3,%YMM11{%K1}

0x4052cf VCVTPS2PD	%YMM11,%ZMM1

0x4052d5 VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

0x4052db VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

0x4052e2 VADDPD	%ZMM3,%ZMM1,%ZMM1

0x4052e8 VEXTRACTF128	$0x1,%YMM1,%XMM3

0x4052ee VADDPD	%XMM3,%XMM1,%XMM1

0x4052f2 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

0x4052f7 VADDSD	%XMM3,%XMM1,%XMM1

0x4052fb VADDSD	%XMM1,%XMM2,%XMM2

0x4052ff VCVTSD2SS	%XMM2,%XMM2,%XMM1

0x405303 VMULSS	0x19c(%RSP),%XMM1,%XMM1

0x40530c LEA	(%RSI,%RDI,1),%R8D

0x405310 MOV	0xa0(%RSP),%R9

0x405318 VMOVSS	%XMM1,(%R9,%R8,4)

0x40531e LEA	0x1(%RDI),%R8

0x405322 CMP	0x188(%RSP),%RDI

0x40532a MOV	%R8,%RDI

0x40532d JE	405200

0x405333 VPBROADCASTD	%EDI,%YMM1

0x405339 TEST	%R15,%R15

0x40533c JE	405240

0x405342 VXORPD	%XMM2,%XMM2,%XMM2

0x405346 XOR	%R8D,%R8D

0x405349 NOPL	(%RAX)

  (28) 0x405350 LEA	(%RCX,%R8,1),%R9D

  (28) 0x405354 VPBROADCASTD	%R9D,%YMM3

  (28) 0x40535a LEA	(%R11,%R14,1),%R9

  (28) 0x40535e VXORPD	%XMM4,%XMM4,%XMM4

  (28) 0x405362 VPCMPEQB	%XMM0,%XMM0,%K1

  (28) 0x405368 VPBROADCASTD	%R8D,%YMM5

  (28) 0x40536e VPADDD	%YMM3,%YMM10,%YMM3

  (28) 0x405372 VPADDD	%YMM5,%YMM8,%YMM5

  (28) 0x405376 VPMULLD	%YMM5,%YMM7,%YMM5

  (28) 0x40537b VPADDD	%YMM5,%YMM1,%YMM5

  (28) 0x40537f LEA	(%R12,%R14,1),%R10

  (28) 0x405383 VPSUBD	%YMM9,%YMM5,%YMM5

  (28) 0x405388 VXORPS	%XMM6,%XMM6,%XMM6

  (28) 0x40538c VGATHERDPS	(%R9,%YMM3,4),%YMM4{%K1}

  (28) 0x405393 VPCMPEQB	%XMM0,%XMM0,%K1

  (28) 0x405399 VGATHERDPS	(%R10,%YMM5,4),%YMM6{%K1}

  (28) 0x4053a0 VCVTPS2PD	%YMM4,%ZMM3

  (28) 0x4053a6 VCVTPS2PD	%YMM6,%ZMM4

  (28) 0x4053ac VFMADD231PD	%ZMM4,%ZMM3,%ZMM2

  (28) 0x4053b2 ADD	$0x8,%R8

  (28) 0x4053b6 CMP	%R15,%R8

  (28) 0x4053b9 JB	405350

0x4053bb VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

0x4053c2 VADDPD	%ZMM3,%ZMM2,%ZMM2

0x4053c8 VEXTRACTF128	$0x1,%YMM2,%XMM3

0x4053ce VADDPD	%XMM3,%XMM2,%XMM2

0x4053d2 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x4053d7 VADDSD	%XMM3,%XMM2,%XMM2

0x4053db MOV	%R15,%R8

0x4053de TEST	$0x1,%AL

0x4053e0 JE	405247

0x4053e6 JMP	4052ff

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 98

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	1.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	11.57
CQA cycles if fully vectorized	8.11
Front-end cycles	12.50
P0 cycles	10.14
P1 cycles	10.03
P2 cycles	8.17
P3 cycles	8.17
P4 cycles	1.00
P5 cycles	10.67
P6 cycles	4.83
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	50.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	1.73
Nb FLOP add-sub	15.33
Nb FLOP mul	6.33
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.72
Bytes prefetched	0.00
Bytes loaded	134.67
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	64.28
Vectorization ratio load	38.10
Vectorization ratio store	0.00
Vectorization ratio mul	44.44
Vectorization ratio add_sub	74.53
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	65.87
Vector-efficiency ratio all	36.88
Vector-efficiency ratio load	29.32
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	36.81
Vector-efficiency ratio add_sub	48.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.89

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.25
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	13.35
CQA cycles if fully vectorized	9.44
Front-end cycles	14.25
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	11.50
P3 cycles	11.50
P4 cycles	1.00
P5 cycles	12.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	57.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	1.47
Nb FLOP add-sub	12.00
Nb FLOP mul	9.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.75
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	73.53
Vectorization ratio load	57.14
Vectorization ratio store	0.00
Vectorization ratio mul	66.67
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	73.68
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	39.29
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	52.08
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	38.16

Metric	Value
CQA speedup if no scalar integer	1.30
CQA speedup if FP arith vectorized	1.09
CQA speedup if fully vectorized	1.57
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.96
CQA cycles if fully vectorized	4.14
Front-end cycles	6.50
P0 cycles	4.75
P1 cycles	4.75
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	4.50
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	26.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.85
Nb FLOP add-sub	11.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.69
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	46.15
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.52
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.09

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.09
CQA speedup if fully vectorized	1.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.75
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.40
CQA cycles if fully vectorized	10.76
Front-end cycles	16.75
P0 cycles	13.67
P1 cycles	13.33
P2 cycles	11.50
P3 cycles	11.50
P4 cycles	1.00
P5 cycles	15.00
P6 cycles	6.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	67.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	1.91
Nb FLOP add-sub	23.00
Nb FLOP mul	9.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.70
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	73.17
Vectorization ratio load	57.14
Vectorization ratio store	0.00
Vectorization ratio mul	66.67
Vectorization ratio add_sub	76.92
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	73.91
Vector-efficiency ratio all	42.38
Vector-efficiency ratio load	39.29
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	52.08
Vector-efficiency ratio add_sub	49.04
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	36.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30-33,98.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 36% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.50 to 8.11 cycles (1.54x speedup).

Details

64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

38% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
74% of SSE/AVX addition or subtraction instructions are used in vector version.
44% of SSE/AVX multiply instructions are used in vector version.
65% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VGATHERDPS: 0 occurrences
VPMULLD: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences
VPMOVQD: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 21.666666666667 FP arithmetical operations:

15.33: addition or subtraction
6.33: multiply

The binary loop is loading 134 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	50
loop length	231.67
used x86 registers	8
used mmx registers	0
used xmm registers	3.67
used ymm registers	7.33
used zmm registers	3.67
nb stack references	5
ADD-SUB / MUL ratio	2.83

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	10.14	10.03	8.17	8.17	1.00	10.67	4.83	1.00
cycles	10.14	10.03	8.17	8.17	1.00	10.67	4.83	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.50
Dispatch	10.67
Data deps.	0.00
Overall L1	12.50

Vectorization ratios

INT

all	47%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	69%
load	44%
store	0%
mul	33%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

INT+FP

all	64%
load	38%
store	0%
mul	44%
add-sub	74%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	65%

Vector efficiency ratios

INT

all	36%
load	32%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	35%
load	25%
store	6%
mul	37%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

INT+FP

all	36%
load	29%
store	6%
mul	36%
add-sub	48%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

7% of peak load performance is reached (9.34 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.38 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 12.00 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.25 to 9.44 cycles (1.51x speedup).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
80% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.02x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 21 FP arithmetical operations:

12: addition or subtraction
9: multiply

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	57
loop length	258
used x86 registers	8
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	4
nb stack references	6
ADD-SUB / MUL ratio	2.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.00	12.00	11.50	11.50	1.00	12.00	4.00	1.00
cycles	12.00	12.00	11.50	11.50	1.00	12.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	14.25
Dispatch	12.00
Data deps.	0.00
Overall L1	14.25

Vectorization ratios

INT

all	73%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	73%
load	66%
store	0%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	91%

INT+FP

all	73%
load	57%
store	0%
mul	66%
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	50%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	38%
load	35%
store	6%
mul	53%
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	43%
load	39%
store	6%
mul	52%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.25 cycles. At this rate:

10% of peak load performance is reached (13.47 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.25 to 12.00 cycles (1.19x speedup).

ASM code

In the binary file, the address of the loop is: 405333

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTQ %R8,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQU64 0x340(%RSP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPCMPGTQ %ZMM13,%ZMM4,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM14,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xc8(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTD 0x8d81(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM12,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x320(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
LEA (%R12,%R14,1),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VMULSS 0x19c(%RSP),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RSI,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xa0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R9,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RDI),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x188(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405200 <main+0x1f50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %EDI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 405240 <main+0x1f90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 5.00 cycles (1.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.50 to 4.14 cycles (1.57x speedup).

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

11: addition or subtraction
1: multiply

The binary loop is loading 20 bytes (5 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.50 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	26
loop length	129
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	2
nb stack references	3
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.75	4.75	1.50	1.50	1.00	5.00	4.50	1.00
cycles	4.75	4.75	1.50	1.50	1.00	5.00	4.50	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.50
Dispatch	5.00
Data deps.	0.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	60%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	46%
load	0%
store	0%
mul	0%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	28%
load	6%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	24%
load	9%
store	6%
mul	6%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

2% of peak load performance is reached (3.08 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405333

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VMULSS 0x19c(%RSP),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RSI,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xa0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R9,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RDI),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x188(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405200 <main+0x1f50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %EDI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 405240 <main+0x1f90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x1,%AL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 405247 <main+0x1f97>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 4052ff <main+0x204f>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.75 to 15.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 42% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.75 to 10.76 cycles (1.56x speedup).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
76% of SSE/AVX addition or subtraction instructions are used in vector version.
66% of SSE/AVX multiply instructions are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.02x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

23: addition or subtraction
9: multiply

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	67
loop length	308
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	5
nb stack references	6
ADD-SUB / MUL ratio	3.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.75 cycles
front end	16.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	13.67	13.33	11.50	11.50	1.00	15.00	6.00	1.00
cycles	13.67	13.33	11.50	11.50	1.00	15.00	6.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	16.75
Dispatch	15.00
Data deps.	0.00
Overall L1	16.75

Vectorization ratios

INT

all	68%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	76%
load	66%
store	0%
mul	50%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

INT+FP

all	73%
load	57%
store	0%
mul	66%
add-sub	76%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	48%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	38%
load	35%
store	6%
mul	53%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

INT+FP

all	42%
load	39%
store	6%
mul	52%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.75 cycles. At this rate:

8% of peak load performance is reached (11.46 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405333

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %R8,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VMOVDQU64 0x340(%RSP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPCMPGTQ %ZMM13,%ZMM4,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPADDD %YMM3,%YMM14,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xc8(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTD 0x8d81(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM12,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x320(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
LEA (%R12,%R14,1),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM11,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
VMULSS 0x19c(%RSP),%XMM1,%XMM1	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
LEA (%RSI,%RDI,1),%R8D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0xa0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R9,%R8,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RDI),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x188(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405200 <main+0x1f50>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %EDI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 405240 <main+0x1f90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x1,%AL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 405247 <main+0x1f97>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround