| Loop Id: 27 | Module: attention-icx-skl512 | Source: attention_v2.cpp:27-98 [...] | Coverage: 11.85% |
|---|
| Loop Id: 27 | Module: attention-icx-skl512 | Source: attention_v2.cpp:27-98 [...] | Coverage: 11.85% |
|---|
0x405240 VXORPD %XMM2,%XMM2,%XMM2 |
0x405244 XOR %R8D,%R8D |
0x405247 VPBROADCASTQ %R8,%ZMM3 |
0x40524d VMOVDQU64 0x340(%RSP),%ZMM4 |
0x405255 VPSUBQ %ZMM3,%ZMM4,%ZMM4 |
0x40525b VPCMPGTQ %ZMM13,%ZMM4,%K1 |
0x405261 VPMOVQD %ZMM3,%YMM3 |
0x405267 VPADDD %YMM3,%YMM14,%YMM3 |
0x40526b VPADDD %YMM3,%YMM0,%YMM4 |
0x40526f MOV 0xc8(%RSP),%R8 |
0x405277 ADD %R14,%R8 |
0x40527a VPBROADCASTD 0x8d81(%RIP),%YMM6 |
0x405283 VPSUBD %YMM6,%YMM4,%YMM4 |
0x405287 VXORPS %XMM5,%XMM5,%XMM5 |
0x40528b KMOVQ %K1,%K2 |
0x405290 VGATHERDPS (%R8,%YMM4,4),%YMM5{%K2} |
0x405297 VMOVAPS %YMM5,%YMM12{%K1} |
0x40529d VCVTPS2PD %YMM12,%ZMM4 |
0x4052a3 VPMULLD 0x320(%RSP),%YMM3,%YMM3 |
0x4052ad VPADDD %YMM3,%YMM1,%YMM1 |
0x4052b1 LEA (%R12,%R14,1),%R8 |
0x4052b5 VPSUBD %YMM6,%YMM1,%YMM1 |
0x4052b9 VPXOR %XMM3,%XMM3,%XMM3 |
0x4052bd KMOVQ %K1,%K2 |
0x4052c2 VGATHERDPS (%R8,%YMM1,4),%YMM3{%K2} |
0x4052c9 VMOVAPS %YMM3,%YMM11{%K1} |
0x4052cf VCVTPS2PD %YMM11,%ZMM1 |
0x4052d5 VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z} |
0x4052db VEXTRACTF64X4 $0x1,%ZMM1,%YMM3 |
0x4052e2 VADDPD %ZMM3,%ZMM1,%ZMM1 |
0x4052e8 VEXTRACTF128 $0x1,%YMM1,%XMM3 |
0x4052ee VADDPD %XMM3,%XMM1,%XMM1 |
0x4052f2 VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 |
0x4052f7 VADDSD %XMM3,%XMM1,%XMM1 |
0x4052fb VADDSD %XMM1,%XMM2,%XMM2 |
0x4052ff VCVTSD2SS %XMM2,%XMM2,%XMM1 |
0x405303 VMULSS 0x19c(%RSP),%XMM1,%XMM1 |
0x40530c LEA (%RSI,%RDI,1),%R8D |
0x405310 MOV 0xa0(%RSP),%R9 |
0x405318 VMOVSS %XMM1,(%R9,%R8,4) |
0x40531e LEA 0x1(%RDI),%R8 |
0x405322 CMP 0x188(%RSP),%RDI |
0x40532a MOV %R8,%RDI |
0x40532d JE 405200 |
0x405333 VPBROADCASTD %EDI,%YMM1 |
0x405339 TEST %R15,%R15 |
0x40533c JE 405240 |
0x405342 VXORPD %XMM2,%XMM2,%XMM2 |
0x405346 XOR %R8D,%R8D |
0x405349 NOPL (%RAX) |
(28) 0x405350 LEA (%RCX,%R8,1),%R9D |
(28) 0x405354 VPBROADCASTD %R9D,%YMM3 |
(28) 0x40535a LEA (%R11,%R14,1),%R9 |
(28) 0x40535e VXORPD %XMM4,%XMM4,%XMM4 |
(28) 0x405362 VPCMPEQB %XMM0,%XMM0,%K1 |
(28) 0x405368 VPBROADCASTD %R8D,%YMM5 |
(28) 0x40536e VPADDD %YMM3,%YMM10,%YMM3 |
(28) 0x405372 VPADDD %YMM5,%YMM8,%YMM5 |
(28) 0x405376 VPMULLD %YMM5,%YMM7,%YMM5 |
(28) 0x40537b VPADDD %YMM5,%YMM1,%YMM5 |
(28) 0x40537f LEA (%R12,%R14,1),%R10 |
(28) 0x405383 VPSUBD %YMM9,%YMM5,%YMM5 |
(28) 0x405388 VXORPS %XMM6,%XMM6,%XMM6 |
(28) 0x40538c VGATHERDPS (%R9,%YMM3,4),%YMM4{%K1} |
(28) 0x405393 VPCMPEQB %XMM0,%XMM0,%K1 |
(28) 0x405399 VGATHERDPS (%R10,%YMM5,4),%YMM6{%K1} |
(28) 0x4053a0 VCVTPS2PD %YMM4,%ZMM3 |
(28) 0x4053a6 VCVTPS2PD %YMM6,%ZMM4 |
(28) 0x4053ac VFMADD231PD %ZMM4,%ZMM3,%ZMM2 |
(28) 0x4053b2 ADD $0x8,%R8 |
(28) 0x4053b6 CMP %R15,%R8 |
(28) 0x4053b9 JB 405350 |
0x4053bb VEXTRACTF64X4 $0x1,%ZMM2,%YMM3 |
0x4053c2 VADDPD %ZMM3,%ZMM2,%ZMM2 |
0x4053c8 VEXTRACTF128 $0x1,%YMM2,%XMM3 |
0x4053ce VADDPD %XMM3,%XMM2,%XMM2 |
0x4053d2 VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 |
0x4053d7 VADDSD %XMM3,%XMM2,%XMM2 |
0x4053db MOV %R15,%R8 |
0x4053de TEST $0x1,%AL |
0x4053e0 JE 405247 |
0x4053e6 JMP 4052ff |
/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 98 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
[...] |
98: if (argc < 4) { |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl512 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.17 |
| CQA speedup if FP arith vectorized | 1.08 |
| CQA speedup if fully vectorized | 1.54 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.17 |
| Bottlenecks | |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.50 |
| CQA cycles if no scalar integer | 10.67 |
| CQA cycles if FP arith vectorized | 11.57 |
| CQA cycles if fully vectorized | 8.11 |
| Front-end cycles | 12.50 |
| P0 cycles | 10.14 |
| P1 cycles | 10.03 |
| P2 cycles | 8.17 |
| P3 cycles | 8.17 |
| P4 cycles | 1.00 |
| P5 cycles | 10.67 |
| P6 cycles | 4.83 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 43.00 |
| Nb uops | 50.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 5.00 |
| FLOP/cycle | 1.73 |
| Nb FLOP add-sub | 15.33 |
| Nb FLOP mul | 6.33 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.72 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 134.67 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 64.28 |
| Vectorization ratio load | 38.10 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 44.44 |
| Vectorization ratio add_sub | 74.53 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 65.87 |
| Vector-efficiency ratio all | 36.88 |
| Vector-efficiency ratio load | 29.32 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 36.81 |
| Vector-efficiency ratio add_sub | 48.29 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 31.89 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.19 |
| CQA speedup if FP arith vectorized | 1.07 |
| CQA speedup if fully vectorized | 1.51 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.19 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 14.25 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 13.35 |
| CQA cycles if fully vectorized | 9.44 |
| Front-end cycles | 14.25 |
| P0 cycles | 12.00 |
| P1 cycles | 12.00 |
| P2 cycles | 11.50 |
| P3 cycles | 11.50 |
| P4 cycles | 1.00 |
| P5 cycles | 12.00 |
| P6 cycles | 4.00 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 47.00 |
| Nb uops | 57.00 |
| Nb loads | 9.00 |
| Nb stores | 1.00 |
| Nb stack references | 6.00 |
| FLOP/cycle | 1.47 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 9.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.75 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 73.53 |
| Vectorization ratio load | 57.14 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 80.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 73.68 |
| Vector-efficiency ratio all | 43.75 |
| Vector-efficiency ratio load | 39.29 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 52.08 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 38.16 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.30 |
| CQA speedup if FP arith vectorized | 1.09 |
| CQA speedup if fully vectorized | 1.57 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.30 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.50 |
| CQA cycles if no scalar integer | 5.00 |
| CQA cycles if FP arith vectorized | 5.96 |
| CQA cycles if fully vectorized | 4.14 |
| Front-end cycles | 6.50 |
| P0 cycles | 4.75 |
| P1 cycles | 4.75 |
| P2 cycles | 1.50 |
| P3 cycles | 1.50 |
| P4 cycles | 1.00 |
| P5 cycles | 5.00 |
| P6 cycles | 4.50 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 25.00 |
| Nb uops | 26.00 |
| Nb loads | 3.00 |
| Nb stores | 1.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 1.85 |
| Nb FLOP add-sub | 11.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 3.69 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 20.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 46.15 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 66.67 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 24.52 |
| Vector-efficiency ratio load | 9.38 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 45.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 21.09 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.12 |
| CQA speedup if FP arith vectorized | 1.09 |
| CQA speedup if fully vectorized | 1.56 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.12 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.75 |
| CQA cycles if no scalar integer | 15.00 |
| CQA cycles if FP arith vectorized | 15.40 |
| CQA cycles if fully vectorized | 10.76 |
| Front-end cycles | 16.75 |
| P0 cycles | 13.67 |
| P1 cycles | 13.33 |
| P2 cycles | 11.50 |
| P3 cycles | 11.50 |
| P4 cycles | 1.00 |
| P5 cycles | 15.00 |
| P6 cycles | 6.00 |
| P7 cycles | 1.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 57.00 |
| Nb uops | 67.00 |
| Nb loads | 9.00 |
| Nb stores | 1.00 |
| Nb stack references | 6.00 |
| FLOP/cycle | 1.91 |
| Nb FLOP add-sub | 23.00 |
| Nb FLOP mul | 9.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.70 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 73.17 |
| Vectorization ratio load | 57.14 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 76.92 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 73.91 |
| Vector-efficiency ratio all | 42.38 |
| Vector-efficiency ratio load | 39.29 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 52.08 |
| Vector-efficiency ratio add_sub | 49.04 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 36.41 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:27-98 |
| Module | attention-icx-skl512 |
| nb instructions | 43 |
| nb uops | 50 |
| loop length | 231.67 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 3.67 |
| used ymm registers | 7.33 |
| used zmm registers | 3.67 |
| nb stack references | 5 |
| ADD-SUB / MUL ratio | 2.83 |
| micro-operation queue | 12.50 cycles |
| front end | 12.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 10.14 | 10.03 | 8.17 | 8.17 | 1.00 | 10.67 | 4.83 | 1.00 |
| cycles | 10.14 | 10.03 | 8.17 | 8.17 | 1.00 | 10.67 | 4.83 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 12.50 |
| Dispatch | 10.67 |
| Data deps. | 0.00 |
| Overall L1 | 12.50 |
| all | 47% |
| load | 33% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 26% |
| all | 69% |
| load | 44% |
| store | 0% |
| mul | 33% |
| add-sub | 57% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 88% |
| all | 64% |
| load | 38% |
| store | 0% |
| mul | 44% |
| add-sub | 74% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 65% |
| all | 36% |
| load | 32% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 50% |
| add-sub | 58% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 27% |
| all | 35% |
| load | 25% |
| store | 6% |
| mul | 37% |
| add-sub | 41% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 34% |
| all | 36% |
| load | 29% |
| store | 6% |
| mul | 36% |
| add-sub | 48% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 31% |
| Function | main |
| Source file and lines | attention_v2.cpp:27-98 |
| Module | attention-icx-skl512 |
| nb instructions | 47 |
| nb uops | 57 |
| loop length | 258 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 9 |
| used zmm registers | 4 |
| nb stack references | 6 |
| ADD-SUB / MUL ratio | 2.00 |
| micro-operation queue | 14.25 cycles |
| front end | 14.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 12.00 | 12.00 | 11.50 | 11.50 | 1.00 | 12.00 | 4.00 | 1.00 |
| cycles | 12.00 | 12.00 | 11.50 | 11.50 | 1.00 | 12.00 | 4.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 14.25 |
| Dispatch | 12.00 |
| Data deps. | 0.00 |
| Overall L1 | 14.25 |
| all | 73% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 42% |
| all | 73% |
| load | 66% |
| store | 0% |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 91% |
| all | 73% |
| load | 57% |
| store | 0% |
| mul | 66% |
| add-sub | 80% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 73% |
| all | 50% |
| load | 42% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 50% |
| add-sub | 58% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 37% |
| all | 38% |
| load | 35% |
| store | 6% |
| mul | 53% |
| add-sub | 37% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 38% |
| all | 43% |
| load | 39% |
| store | 6% |
| mul | 52% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 38% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| VPBROADCASTQ %R8,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVDQU64 0x340(%RSP),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPSUBQ %ZMM3,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | vect (100.0%) |
| VPCMPGTQ %ZMM13,%ZMM4,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VPMOVQD %ZMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VPADDD %YMM3,%YMM14,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDD %YMM3,%YMM0,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPBROADCASTD 0x8d81(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VPSUBD %YMM6,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VXORPS %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VGATHERDPS (%R8,%YMM4,4),%YMM5{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 | vect (50.0%) |
| VMOVAPS %YMM5,%YMM12{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VCVTPS2PD %YMM12,%ZMM4 | 2 | 0.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 7 | 1 | vect (50.0%) |
| VPMULLD 0x320(%RSP),%YMM3,%YMM3 | 3 | 1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 1 | vect (50.0%) |
| VPADDD %YMM3,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| LEA (%R12,%R14,1),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VPSUBD %YMM6,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPXOR %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VGATHERDPS (%R8,%YMM1,4),%YMM3{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 | vect (50.0%) |
| VMOVAPS %YMM3,%YMM11{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VCVTPS2PD %YMM11,%ZMM1 | 2 | 0.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 7 | 1 | vect (50.0%) |
| VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF64X4 $0x1,%ZMM1,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM3,%ZMM1,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF128 $0x1,%YMM1,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | vect (25.0%) |
| VADDSD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM1,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSD2SS %XMM2,%XMM2,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| VMULSS 0x19c(%RSP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| LEA (%RSI,%RDI,1),%R8D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV 0xa0(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM1,(%R9,%R8,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| LEA 0x1(%RDI),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| CMP 0x188(%RSP),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| JE 405200 <main+0x1f50> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VPBROADCASTD %EDI,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (6.3%) |
| TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JE 405240 <main+0x1f90> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:27-98 |
| Module | attention-icx-skl512 |
| nb instructions | 25 |
| nb uops | 26 |
| loop length | 129 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 3 |
| used zmm registers | 2 |
| nb stack references | 3 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.75 | 4.75 | 1.50 | 1.50 | 1.00 | 5.00 | 4.50 | 1.00 |
| cycles | 4.75 | 4.75 | 1.50 | 1.50 | 1.00 | 5.00 | 4.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 6.50 |
| Dispatch | 5.00 |
| Data deps. | 0.00 |
| Overall L1 | 6.50 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 60% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 80% |
| all | 46% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 66% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 10% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 28% |
| load | 6% |
| store | 6% |
| mul | 6% |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 27% |
| all | 24% |
| load | 9% |
| store | 6% |
| mul | 6% |
| add-sub | 45% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 21% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM2,%XMM2,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| VMULSS 0x19c(%RSP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| LEA (%RSI,%RDI,1),%R8D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV 0xa0(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM1,(%R9,%R8,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| LEA 0x1(%RDI),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| CMP 0x188(%RSP),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| JE 405200 <main+0x1f50> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VPBROADCASTD %EDI,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (6.3%) |
| TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| JE 405240 <main+0x1f90> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| VEXTRACTF64X4 $0x1,%ZMM2,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM3,%ZMM2,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | vect (25.0%) |
| VADDSD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV %R15,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| TEST $0x1,%AL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JE 405247 <main+0x1f97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| JMP 4052ff <main+0x204f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:27-98 |
| Module | attention-icx-skl512 |
| nb instructions | 57 |
| nb uops | 67 |
| loop length | 308 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 10 |
| used zmm registers | 5 |
| nb stack references | 6 |
| ADD-SUB / MUL ratio | 3.50 |
| micro-operation queue | 16.75 cycles |
| front end | 16.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 13.67 | 13.33 | 11.50 | 11.50 | 1.00 | 15.00 | 6.00 | 1.00 |
| cycles | 13.67 | 13.33 | 11.50 | 11.50 | 1.00 | 15.00 | 6.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 16.75 |
| Dispatch | 15.00 |
| Data deps. | 0.00 |
| Overall L1 | 16.75 |
| all | 68% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 37% |
| all | 76% |
| load | 66% |
| store | 0% |
| mul | 50% |
| add-sub | 57% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 93% |
| all | 73% |
| load | 57% |
| store | 0% |
| mul | 66% |
| add-sub | 76% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 73% |
| all | 48% |
| load | 42% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 50% |
| add-sub | 58% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 34% |
| all | 38% |
| load | 35% |
| store | 6% |
| mul | 53% |
| add-sub | 41% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 37% |
| all | 42% |
| load | 39% |
| store | 6% |
| mul | 52% |
| add-sub | 49% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 36% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPBROADCASTQ %R8,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VMOVDQU64 0x340(%RSP),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPSUBQ %ZMM3,%ZMM4,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | vect (100.0%) |
| VPCMPGTQ %ZMM13,%ZMM4,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VPMOVQD %ZMM3,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (100.0%) |
| VPADDD %YMM3,%YMM14,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDD %YMM3,%YMM0,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| MOV 0xc8(%RSP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| ADD %R14,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VPBROADCASTD 0x8d81(%RIP),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VPSUBD %YMM6,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VXORPS %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VGATHERDPS (%R8,%YMM4,4),%YMM5{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 | vect (50.0%) |
| VMOVAPS %YMM5,%YMM12{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VCVTPS2PD %YMM12,%ZMM4 | 2 | 0.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 7 | 1 | vect (50.0%) |
| VPMULLD 0x320(%RSP),%YMM3,%YMM3 | 3 | 1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 1 | vect (50.0%) |
| VPADDD %YMM3,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| LEA (%R12,%R14,1),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| VPSUBD %YMM6,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPXOR %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| KMOVQ %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VGATHERDPS (%R8,%YMM1,4),%YMM3{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 | vect (50.0%) |
| VMOVAPS %YMM3,%YMM11{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| VCVTPS2PD %YMM11,%ZMM1 | 2 | 0.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 7 | 1 | vect (50.0%) |
| VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF64X4 $0x1,%ZMM1,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM3,%ZMM1,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF128 $0x1,%YMM1,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | vect (25.0%) |
| VADDSD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VADDSD %XMM1,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSD2SS %XMM2,%XMM2,%XMM1 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 5 | 1 | scal (12.5%) |
| VMULSS 0x19c(%RSP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| LEA (%RSI,%RDI,1),%R8D | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV 0xa0(%RSP),%R9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVSS %XMM1,(%R9,%R8,4) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (6.3%) |
| LEA 0x1(%RDI),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| CMP 0x188(%RSP),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| JE 405200 <main+0x1f50> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VPBROADCASTD %EDI,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (6.3%) |
| TEST %R15,%R15 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| JE 405240 <main+0x1f90> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VXORPD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (25.0%) |
| XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| VEXTRACTF64X4 $0x1,%ZMM2,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VADDPD %ZMM3,%ZMM2,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| VEXTRACTF128 $0x1,%YMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VADDPD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (25.0%) |
| VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | vect (25.0%) |
| VADDSD %XMM3,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV %R15,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| TEST $0x1,%AL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JE 405247 <main+0x1f97> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
