OV - attention-icx-skl512 - Loop 26

0x405200 LEA	0x1(%RDX),%ESI

0x405203 MOV	0xb8(%RSP),%RDI

0x40520b ADD	%RDI,%RCX

0x40520e CMP	0xac(%RSP),%EDX

0x405215 MOV	%ESI,%EDX

0x405217 JE	4053f0

0x40521d MOV	%EDX,%ESI

0x40521f IMUL	%EDI,%ESI

0x405222 VPBROADCASTD	%ESI,%YMM0

0x405228 MOV	%EDX,%ESI

0x40522a IMUL	0x120(%RSP),%ESI

0x405232 XOR	%EDI,%EDI

0x405234 JMP	405333

  (27) 0x405240 VXORPD	%XMM2,%XMM2,%XMM2

  (27) 0x405244 XOR	%R8D,%R8D

  (27) 0x405247 VPBROADCASTQ	%R8,%ZMM3

  (27) 0x40524d VMOVDQU64	0x340(%RSP),%ZMM4

  (27) 0x405255 VPSUBQ	%ZMM3,%ZMM4,%ZMM4

  (27) 0x40525b VPCMPGTQ	%ZMM13,%ZMM4,%K1

  (27) 0x405261 VPMOVQD	%ZMM3,%YMM3

  (27) 0x405267 VPADDD	%YMM3,%YMM14,%YMM3

  (27) 0x40526b VPADDD	%YMM3,%YMM0,%YMM4

  (27) 0x40526f MOV	0xc8(%RSP),%R8

  (27) 0x405277 ADD	%R14,%R8

  (27) 0x40527a VPBROADCASTD	0x8d81(%RIP),%YMM6

  (27) 0x405283 VPSUBD	%YMM6,%YMM4,%YMM4

  (27) 0x405287 VXORPS	%XMM5,%XMM5,%XMM5

  (27) 0x40528b KMOVQ	%K1,%K2

  (27) 0x405290 VGATHERDPS	(%R8,%YMM4,4),%YMM5{%K2}

  (27) 0x405297 VMOVAPS	%YMM5,%YMM12{%K1}

  (27) 0x40529d VCVTPS2PD	%YMM12,%ZMM4

  (27) 0x4052a3 VPMULLD	0x320(%RSP),%YMM3,%YMM3

  (27) 0x4052ad VPADDD	%YMM3,%YMM1,%YMM1

  (27) 0x4052b1 LEA	(%R12,%R14,1),%R8

  (27) 0x4052b5 VPSUBD	%YMM6,%YMM1,%YMM1

  (27) 0x4052b9 VPXOR	%XMM3,%XMM3,%XMM3

  (27) 0x4052bd KMOVQ	%K1,%K2

  (27) 0x4052c2 VGATHERDPS	(%R8,%YMM1,4),%YMM3{%K2}

  (27) 0x4052c9 VMOVAPS	%YMM3,%YMM11{%K1}

  (27) 0x4052cf VCVTPS2PD	%YMM11,%ZMM1

  (27) 0x4052d5 VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

  (27) 0x4052db VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

  (27) 0x4052e2 VADDPD	%ZMM3,%ZMM1,%ZMM1

  (27) 0x4052e8 VEXTRACTF128	$0x1,%YMM1,%XMM3

  (27) 0x4052ee VADDPD	%XMM3,%XMM1,%XMM1

  (27) 0x4052f2 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

  (27) 0x4052f7 VADDSD	%XMM3,%XMM1,%XMM1

  (27) 0x4052fb VADDSD	%XMM1,%XMM2,%XMM2

  (27) 0x4052ff VCVTSD2SS	%XMM2,%XMM2,%XMM1

  (27) 0x405303 VMULSS	0x19c(%RSP),%XMM1,%XMM1

  (27) 0x40530c LEA	(%RSI,%RDI,1),%R8D

  (27) 0x405310 MOV	0xa0(%RSP),%R9

  (27) 0x405318 VMOVSS	%XMM1,(%R9,%R8,4)

  (27) 0x40531e LEA	0x1(%RDI),%R8

  (27) 0x405322 CMP	0x188(%RSP),%RDI

  (27) 0x40532a MOV	%R8,%RDI

  (27) 0x40532d JE	405200

  (27) 0x405333 VPBROADCASTD	%EDI,%YMM1

  (27) 0x405339 TEST	%R15,%R15

  (27) 0x40533c JE	405240

  (27) 0x405342 VXORPD	%XMM2,%XMM2,%XMM2

  (27) 0x405346 XOR	%R8D,%R8D

  (27) 0x405349 NOPL	(%RAX)

    (28) 0x405350 LEA	(%RCX,%R8,1),%R9D

    (28) 0x405354 VPBROADCASTD	%R9D,%YMM3

    (28) 0x40535a LEA	(%R11,%R14,1),%R9

    (28) 0x40535e VXORPD	%XMM4,%XMM4,%XMM4

    (28) 0x405362 VPCMPEQB	%XMM0,%XMM0,%K1

    (28) 0x405368 VPBROADCASTD	%R8D,%YMM5

    (28) 0x40536e VPADDD	%YMM3,%YMM10,%YMM3

    (28) 0x405372 VPADDD	%YMM5,%YMM8,%YMM5

    (28) 0x405376 VPMULLD	%YMM5,%YMM7,%YMM5

    (28) 0x40537b VPADDD	%YMM5,%YMM1,%YMM5

    (28) 0x40537f LEA	(%R12,%R14,1),%R10

    (28) 0x405383 VPSUBD	%YMM9,%YMM5,%YMM5

    (28) 0x405388 VXORPS	%XMM6,%XMM6,%XMM6

    (28) 0x40538c VGATHERDPS	(%R9,%YMM3,4),%YMM4{%K1}

    (28) 0x405393 VPCMPEQB	%XMM0,%XMM0,%K1

    (28) 0x405399 VGATHERDPS	(%R10,%YMM5,4),%YMM6{%K1}

    (28) 0x4053a0 VCVTPS2PD	%YMM4,%ZMM3

    (28) 0x4053a6 VCVTPS2PD	%YMM6,%ZMM4

    (28) 0x4053ac VFMADD231PD	%ZMM4,%ZMM3,%ZMM2

    (28) 0x4053b2 ADD	$0x8,%R8

    (28) 0x4053b6 CMP	%R15,%R8

    (28) 0x4053b9 JB	405350

  (27) 0x4053bb VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

  (27) 0x4053c2 VADDPD	%ZMM3,%ZMM2,%ZMM2

  (27) 0x4053c8 VEXTRACTF128	$0x1,%YMM2,%XMM3

  (27) 0x4053ce VADDPD	%XMM3,%XMM2,%XMM2

  (27) 0x4053d2 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (27) 0x4053d7 VADDSD	%XMM3,%XMM2,%XMM2

  (27) 0x4053db MOV	%R15,%R8

  (27) 0x4053de TEST	$0x1,%AL

  (27) 0x4053e0 JE	405247

  (27) 0x4053e6 JMP	4052ff

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 98

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.23
Front-end cycles	3.25
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	3.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.23
Front-end cycles	3.25
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	13
nb uops	13
loop length	57
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	1.50	1.50	0.00	2.00	2.00	0.00
cycles	2.00	3.00	1.50	1.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.25
Dispatch	3.00
Data deps.	0.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

3% of peak load performance is reached (4.92 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 3.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 40521d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%ESI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RDI,%RCX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%EDX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0.25	N/A
JE 4053f0 <main+0x2140>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %EDI,%ESI	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %ESI,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL 0x120(%RSP),%ESI	1	0	1	0.50	0.50	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 405333 <main+0x2083>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	13
nb uops	13
loop length	57
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	1.50	1.50	0.00	2.00	2.00	0.00
cycles	2.00	3.00	1.50	1.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.25
Dispatch	3.00
Data deps.	0.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

3% of peak load performance is reached (4.92 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 3.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 40521d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDX),%ESI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RDI,%RCX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%EDX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0.25	N/A
JE 4053f0 <main+0x2140>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %EDI,%ESI	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %ESI,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL 0x120(%RSP),%ESI	1	0	1	0.50	0.50	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 405333 <main+0x2083>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code