OV - attention-icx-skl512 - Loop 20

	Loop Id: 20	Module: attention-icx-skl512	Source: attention_v2.cpp:27-98 [...]	Coverage: 4.38%

0x405a60 VXORPD	%XMM2,%XMM2,%XMM2

0x405a64 XOR	%EDI,%EDI

0x405a66 MOV	0xe0(%RSP),%R8

0x405a6e SUB	%RDI,%R8

0x405a71 VPBROADCASTQ	%R8,%ZMM3

0x405a77 VPCMPGTQ	%ZMM10,%ZMM3,%K1

0x405a7d VPBROADCASTD	%EDI,%YMM3

0x405a83 VPADDD	%YMM3,%YMM11,%YMM3

0x405a87 VPADDD	%YMM3,%YMM0,%YMM4

0x405a8b MOV	0x78(%RSP),%RDI

0x405a90 ADD	%R14,%RDI

0x405a93 VPBROADCASTD	0x8568(%RIP),%YMM6

0x405a9c VPSUBD	%YMM6,%YMM4,%YMM4

0x405aa0 VPXOR	%XMM5,%XMM5,%XMM5

0x405aa4 KMOVQ	%K1,%K2

0x405aa9 VGATHERDPS	(%RDI,%YMM4,4),%YMM5{%K2}

0x405ab0 VMOVAPS	%YMM5,%YMM9{%K1}

0x405ab6 VCVTPS2PD	%YMM9,%ZMM4

0x405abc VPMULLD	0x1c0(%RSP),%YMM3,%YMM3

0x405ac6 VPADDD	%YMM3,%YMM1,%YMM1

0x405aca MOV	0xe8(%RSP),%RDI

0x405ad2 LEA	(%RDI,%R14,1),%RDI

0x405ad6 VPSUBD	%YMM6,%YMM1,%YMM1

0x405ada VPXOR	%XMM3,%XMM3,%XMM3

0x405ade KMOVQ	%K1,%K2

0x405ae3 VGATHERDPS	(%RDI,%YMM1,4),%YMM3{%K2}

0x405aea VMOVAPS	%YMM3,%YMM8{%K1}

0x405af0 VCVTPS2PD	%YMM8,%ZMM1

0x405af6 VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

0x405afc VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

0x405b03 VADDPD	%ZMM3,%ZMM1,%ZMM1

0x405b09 VEXTRACTF128	$0x1,%YMM1,%XMM3

0x405b0f VADDPD	%XMM3,%XMM1,%XMM1

0x405b13 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

0x405b18 VADDSD	%XMM3,%XMM1,%XMM1

0x405b1c VADDSD	%XMM1,%XMM2,%XMM2

0x405b20 VCVTSD2SS	%XMM2,%XMM2,%XMM1

0x405b24 LEA	(%RDX,%RSI,1),%EDI

0x405b27 MOV	0x108(%RSP),%R8

0x405b2f VMOVSS	%XMM1,(%R8,%RDI,4)

0x405b35 LEA	0x1(%RSI),%RDI

0x405b39 CMP	%R10,%RSI

0x405b3c MOV	%RDI,%RSI

0x405b3f JE	405a20

0x405b45 VPBROADCASTD	%ESI,%YMM1

0x405b4b TEST	%R9,%R9

0x405b4e JE	405a60

0x405b54 VXORPD	%XMM2,%XMM2,%XMM2

0x405b58 XOR	%EDI,%EDI

0x405b5a VMOVDQU	0x1c0(%RSP),%YMM5

0x405b63 VPMOVSXBD	0x8754(%RIP),%YMM6

0x405b6c MOV	0x78(%RSP),%R12

0x405b71 NOPW	%CS:(%RAX,%RAX,1)

  (21) 0x405b80 VPBROADCASTD	%EDI,%YMM3

  (21) 0x405b86 VPADDD	%YMM6,%YMM3,%YMM3

  (21) 0x405b8a VPMULLD	%YMM3,%YMM5,%YMM3

  (21) 0x405b8f VPADDD	%YMM3,%YMM1,%YMM3

  (21) 0x405b93 LEA	(%R11,%R14,1),%R8

  (21) 0x405b97 VPCMPEQB	%XMM0,%XMM0,%K1

  (21) 0x405b9d VPSUBD	%YMM7,%YMM3,%YMM3

  (21) 0x405ba1 VXORPD	%XMM4,%XMM4,%XMM4

  (21) 0x405ba5 VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}

  (21) 0x405bac LEA	(%RAX,%RDI,1),%R8D

  (21) 0x405bb0 VCVTPS2PD	(%R12,%R8,4),%ZMM3

  (21) 0x405bb7 VCVTPS2PD	%YMM4,%ZMM4

  (21) 0x405bbd VFMADD231PD	%ZMM4,%ZMM3,%ZMM2

  (21) 0x405bc3 ADD	$0x8,%RDI

  (21) 0x405bc7 CMP	%R9,%RDI

  (21) 0x405bca JB	405b80

0x405bcc VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

0x405bd3 VADDPD	%ZMM3,%ZMM2,%ZMM2

0x405bd9 VEXTRACTF128	$0x1,%YMM2,%XMM3

0x405bdf VADDPD	%XMM3,%XMM2,%XMM2

0x405be3 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0x405be8 VADDSD	%XMM3,%XMM2,%XMM2

0x405bec MOV	%R9,%RDI

0x405bef CMP	%R9,0xe0(%RSP)

0x405bf7 MOV	0x130(%RSP),%R12

0x405bff JNE	405a66

0x405c05 JMP	405b20

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 98

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	1.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.33
CQA cycles if no scalar integer	11.33
CQA cycles if FP arith vectorized	12.52
CQA cycles if fully vectorized	8.38
Front-end cycles	13.33
P0 cycles	9.39
P1 cycles	9.19
P2 cycles	9.17
P3 cycles	9.17
P4 cycles	1.00
P5 cycles	11.33
P6 cycles	5.75
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.33
Nb uops	53.33
Nb loads	9.00
Nb stores	1.00
Nb stack references	5.33
FLOP/cycle	1.55
Nb FLOP add-sub	15.33
Nb FLOP mul	5.33
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.21
Bytes prefetched	0.00
Bytes loaded	133.33
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	63.34
Vectorization ratio load	62.50
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	73.15
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	62.66
Vector-efficiency ratio all	33.21
Vector-efficiency ratio load	30.47
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	45.02
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.88

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	1.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.25
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	13.49
CQA cycles if fully vectorized	9.44
Front-end cycles	14.25
P0 cycles	11.00
P1 cycles	11.00
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	1.00
P5 cycles	12.00
P6 cycles	5.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	57.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	1.40
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.54
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.97
Vectorization ratio load	75.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	77.78
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	68.42
Vector-efficiency ratio all	38.31
Vector-efficiency ratio load	39.06
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	44.44
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.22

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.06
CQA cycles if fully vectorized	4.49
Front-end cycles	7.50
P0 cycles	4.50
P1 cycles	4.25
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	6.00
P6 cycles	4.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	30.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	1.47
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.13
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	50.00
Vectorization ratio load	50.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	21.88
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.09

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.25
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	17.02
CQA cycles if fully vectorized	11.22
Front-end cycles	18.25
P0 cycles	12.67
P1 cycles	12.33
P2 cycles	13.50
P3 cycles	13.50
P4 cycles	1.00
P5 cycles	16.00
P6 cycles	8.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	73.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	1.70
Nb FLOP add-sub	23.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.96
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	69.05
Vectorization ratio load	62.50
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	69.57
Vector-efficiency ratio all	36.31
Vector-efficiency ratio load	30.47
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	75.00
Vector-efficiency ratio add_sub	44.79
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.34

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30-33,98.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 33% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.33 to 8.38 cycles (1.59x speedup).

Details

63% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

62% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
73% of SSE/AVX addition or subtraction instructions are used in vector version.
62% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VGATHERDPS: 0 occurrences
VPMULLD: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20.666666666667 FP arithmetical operations:

15.33: addition or subtraction
5.33: multiply

The binary loop is loading 133 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	45.33
nb uops	53.33
loop length	247
used x86 registers	9
used mmx registers	0
used xmm registers	3.67
used ymm registers	8
used zmm registers	3.67
nb stack references	5.33
ADD-SUB / MUL ratio	5.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	13.33 cycles
front end	13.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	9.39	9.19	9.17	9.17	1.00	11.33	5.75	1.00
cycles	9.39	9.19	9.17	9.17	1.00	11.33	5.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	13.33
Dispatch	11.33
Data deps.	0.00
Overall L1	13.33

Vectorization ratios

INT

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	73%
load	100%
store	0%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	87%

INT+FP

all	63%
load	62%
store	0%
mul	100%
add-sub	73%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	62%

Vector efficiency ratios

INT

all	27%
load	24%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	37%
load	50%
store	6%
mul	100%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

INT+FP

all	33%
load	30%
store	6%
mul	75%
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.33 cycles. At this rate:

7% of peak load performance is reached (9.87 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.34 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.25 to 12.00 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.25 to 9.44 cycles (1.51x speedup).

Details

70% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
77% of SSE/AVX addition or subtraction instructions are used in vector version.
68% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.02x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction
8: multiply

The binary loop is loading 132 bytes (16 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	57
loop length	244
used x86 registers	8
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	4
nb stack references	5
ADD-SUB / MUL ratio	4.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.25 cycles
front end	14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	11.00	11.00	11.00	11.00	1.00	12.00	5.00	1.00
cycles	11.00	11.00	11.00	11.00	1.00	12.00	5.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	14.25
Dispatch	12.00
Data deps.	0.00
Overall L1	14.25

Vectorization ratios

INT

all	64%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	76%
load	100%
store	0%
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	70%
load	75%
store	0%
mul	100%
add-sub	77%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	68%

Vector efficiency ratios

INT

all	35%
load	28%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	24%

all	40%
load	50%
store	6%
mul	100%
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

INT+FP

all	38%
load	39%
store	6%
mul	75%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.25 cycles. At this rate:

7% of peak load performance is reached (9.26 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.28 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.25 to 12.00 cycles (1.19x speedup).

ASM code

In the binary file, the address of the loop is: 405b45

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xe0(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RDI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTQ %R8,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VPCMPGTQ %ZMM10,%ZMM3,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPBROADCASTD %EDI,%YMM3	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM11,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0x78(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTD 0x8568(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM9,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x1c0(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xe8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RDI,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM8{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM8,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x108(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R10,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405a20 <main+0x2770>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R9,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 405a60 <main+0x27b0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.50 to 4.49 cycles (1.67x speedup).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

11: addition or subtraction

The binary loop is loading 72 bytes (9 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	30
loop length	158
used x86 registers	9
used mmx registers	0
used xmm registers	3
used ymm registers	5
used zmm registers	2
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.50	4.25	3.00	3.00	1.00	6.00	4.25	1.00
cycles	4.50	4.25	3.00	3.00	1.00	6.00	4.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.50
Dispatch	6.00
Data deps.	0.00
Overall L1	7.50

Vectorization ratios

INT

all	28%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	50%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	16%
load	21%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	25%
load	21%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

7% of peak load performance is reached (9.60 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.53 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405b45

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x108(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R10,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405a20 <main+0x2770>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R9,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 405a60 <main+0x27b0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x1c0(%RSP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VPMOVSXBD 0x8754(%RIP),%YMM6	2	0	0	0.50	0.50	0	1	0	0	3	1	vect (12.5%)
MOV 0x78(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R9,0xe0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV 0x130(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JNE 405a66 <main+0x27b6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 405b20 <main+0x2870>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-icx-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.25 to 16.00 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 36% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.25 to 11.22 cycles (1.63x speedup).

Details

69% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

62% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
75% of SSE/AVX addition or subtraction instructions are used in vector version.
69% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMOVSXBD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:30

Workaround

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

23: addition or subtraction
8: multiply

The binary loop is loading 196 bytes (24 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	61
nb uops	73
loop length	339
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	5
nb stack references	6
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.25 cycles
front end	18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.67	12.33	13.50	13.50	1.00	16.00	8.00	1.00
cycles	12.67	12.33	13.50	13.50	1.00	16.00	8.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.25
Dispatch	16.00
Data deps.	0.00
Overall L1	18.25

Vectorization ratios

INT

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	78%
load	100%
store	0%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	92%

INT+FP

all	69%
load	62%
store	0%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	69%

Vector efficiency ratios

INT

all	31%
load	23%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	40%
load	50%
store	6%
mul	100%
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

INT+FP

all	36%
load	30%
store	6%
mul	75%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.25 cycles. At this rate:

8% of peak load performance is reached (10.74 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.22 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405b45

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xe0(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
SUB %RDI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTQ %R8,%ZMM3	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
VPCMPGTQ %ZMM10,%ZMM3,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPBROADCASTD %EDI,%YMM3	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM11,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0x78(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R14,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VPBROADCASTD 0x8568(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM5,%YMM9{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM9,%ZMM4	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VPMULLD 0x1c0(%RSP),%YMM3,%YMM3	3	1	1	0.50	0.50	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
MOV 0xe8(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RDI,%R14,1),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %YMM6,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%RDI,%YMM1,4),%YMM3{%K2}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
VMOVAPS %YMM3,%YMM8{%K1}	1	0	0	0	0	0	0	0	0	0	0.25	vect (50.0%)
VCVTPS2PD %YMM8,%ZMM1	2	0.50	0	0	0	0	1.50	0	0	7	1	vect (50.0%)
VMULPD %ZMM4,%ZMM1,%ZMM1{%K1}{z}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCVTSD2SS %XMM2,%XMM2,%XMM1	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x108(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP %R10,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 405a20 <main+0x2770>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTD %ESI,%YMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
TEST %R9,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 405a60 <main+0x27b0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x1c0(%RSP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (50.0%)
VPMOVSXBD 0x8754(%RIP),%YMM6	2	0	0	0.50	0.50	0	1	0	0	3	1	vect (12.5%)
MOV 0x78(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF64X4 $0x1,%ZMM2,%YMM3	1	0	0	0	0	0	1	0	0	3	1	vect (50.0%)
VADDPD %ZMM3,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM3	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM3,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R9,0xe0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
MOV 0x130(%RSP),%R12	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JNE 405a66 <main+0x27b6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop