OV - attention-icx-skl512 - Loop 19

0x405a20 LEA	0x1(%RCX),%EDX

0x405a23 MOV	0x120(%RSP),%RSI

0x405a2b ADD	%RSI,%RAX

0x405a2e CMP	0xac(%RSP),%ECX

0x405a35 MOV	%EDX,%ECX

0x405a37 JE	405c10

0x405a3d MOV	%ECX,%EDX

0x405a3f IMUL	%ESI,%EDX

0x405a42 VPBROADCASTD	%EDX,%YMM0

0x405a48 MOV	%ECX,%EDX

0x405a4a IMUL	0xb8(%RSP),%EDX

0x405a52 XOR	%ESI,%ESI

0x405a54 JMP	405b45

  (20) 0x405a60 VXORPD	%XMM2,%XMM2,%XMM2

  (20) 0x405a64 XOR	%EDI,%EDI

  (20) 0x405a66 MOV	0xe0(%RSP),%R8

  (20) 0x405a6e SUB	%RDI,%R8

  (20) 0x405a71 VPBROADCASTQ	%R8,%ZMM3

  (20) 0x405a77 VPCMPGTQ	%ZMM10,%ZMM3,%K1

  (20) 0x405a7d VPBROADCASTD	%EDI,%YMM3

  (20) 0x405a83 VPADDD	%YMM3,%YMM11,%YMM3

  (20) 0x405a87 VPADDD	%YMM3,%YMM0,%YMM4

  (20) 0x405a8b MOV	0x78(%RSP),%RDI

  (20) 0x405a90 ADD	%R14,%RDI

  (20) 0x405a93 VPBROADCASTD	0x8568(%RIP),%YMM6

  (20) 0x405a9c VPSUBD	%YMM6,%YMM4,%YMM4

  (20) 0x405aa0 VPXOR	%XMM5,%XMM5,%XMM5

  (20) 0x405aa4 KMOVQ	%K1,%K2

  (20) 0x405aa9 VGATHERDPS	(%RDI,%YMM4,4),%YMM5{%K2}

  (20) 0x405ab0 VMOVAPS	%YMM5,%YMM9{%K1}

  (20) 0x405ab6 VCVTPS2PD	%YMM9,%ZMM4

  (20) 0x405abc VPMULLD	0x1c0(%RSP),%YMM3,%YMM3

  (20) 0x405ac6 VPADDD	%YMM3,%YMM1,%YMM1

  (20) 0x405aca MOV	0xe8(%RSP),%RDI

  (20) 0x405ad2 LEA	(%RDI,%R14,1),%RDI

  (20) 0x405ad6 VPSUBD	%YMM6,%YMM1,%YMM1

  (20) 0x405ada VPXOR	%XMM3,%XMM3,%XMM3

  (20) 0x405ade KMOVQ	%K1,%K2

  (20) 0x405ae3 VGATHERDPS	(%RDI,%YMM1,4),%YMM3{%K2}

  (20) 0x405aea VMOVAPS	%YMM3,%YMM8{%K1}

  (20) 0x405af0 VCVTPS2PD	%YMM8,%ZMM1

  (20) 0x405af6 VMULPD	%ZMM4,%ZMM1,%ZMM1{%K1}{z}

  (20) 0x405afc VEXTRACTF64X4	$0x1,%ZMM1,%YMM3

  (20) 0x405b03 VADDPD	%ZMM3,%ZMM1,%ZMM1

  (20) 0x405b09 VEXTRACTF128	$0x1,%YMM1,%XMM3

  (20) 0x405b0f VADDPD	%XMM3,%XMM1,%XMM1

  (20) 0x405b13 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

  (20) 0x405b18 VADDSD	%XMM3,%XMM1,%XMM1

  (20) 0x405b1c VADDSD	%XMM1,%XMM2,%XMM2

  (20) 0x405b20 VCVTSD2SS	%XMM2,%XMM2,%XMM1

  (20) 0x405b24 LEA	(%RDX,%RSI,1),%EDI

  (20) 0x405b27 MOV	0x108(%RSP),%R8

  (20) 0x405b2f VMOVSS	%XMM1,(%R8,%RDI,4)

  (20) 0x405b35 LEA	0x1(%RSI),%RDI

  (20) 0x405b39 CMP	%R10,%RSI

  (20) 0x405b3c MOV	%RDI,%RSI

  (20) 0x405b3f JE	405a20

  (20) 0x405b45 VPBROADCASTD	%ESI,%YMM1

  (20) 0x405b4b TEST	%R9,%R9

  (20) 0x405b4e JE	405a60

  (20) 0x405b54 VXORPD	%XMM2,%XMM2,%XMM2

  (20) 0x405b58 XOR	%EDI,%EDI

  (20) 0x405b5a VMOVDQU	0x1c0(%RSP),%YMM5

  (20) 0x405b63 VPMOVSXBD	0x8754(%RIP),%YMM6

  (20) 0x405b6c MOV	0x78(%RSP),%R12

  (20) 0x405b71 NOPW	%CS:(%RAX,%RAX,1)

    (21) 0x405b80 VPBROADCASTD	%EDI,%YMM3

    (21) 0x405b86 VPADDD	%YMM6,%YMM3,%YMM3

    (21) 0x405b8a VPMULLD	%YMM3,%YMM5,%YMM3

    (21) 0x405b8f VPADDD	%YMM3,%YMM1,%YMM3

    (21) 0x405b93 LEA	(%R11,%R14,1),%R8

    (21) 0x405b97 VPCMPEQB	%XMM0,%XMM0,%K1

    (21) 0x405b9d VPSUBD	%YMM7,%YMM3,%YMM3

    (21) 0x405ba1 VXORPD	%XMM4,%XMM4,%XMM4

    (21) 0x405ba5 VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}

    (21) 0x405bac LEA	(%RAX,%RDI,1),%R8D

    (21) 0x405bb0 VCVTPS2PD	(%R12,%R8,4),%ZMM3

    (21) 0x405bb7 VCVTPS2PD	%YMM4,%ZMM4

    (21) 0x405bbd VFMADD231PD	%ZMM4,%ZMM3,%ZMM2

    (21) 0x405bc3 ADD	$0x8,%RDI

    (21) 0x405bc7 CMP	%R9,%RDI

    (21) 0x405bca JB	405b80

  (20) 0x405bcc VEXTRACTF64X4	$0x1,%ZMM2,%YMM3

  (20) 0x405bd3 VADDPD	%ZMM3,%ZMM2,%ZMM2

  (20) 0x405bd9 VEXTRACTF128	$0x1,%YMM2,%XMM3

  (20) 0x405bdf VADDPD	%XMM3,%XMM2,%XMM2

  (20) 0x405be3 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (20) 0x405be8 VADDSD	%XMM3,%XMM2,%XMM2

  (20) 0x405bec MOV	%R9,%RDI

  (20) 0x405bef CMP	%R9,0xe0(%RSP)

  (20) 0x405bf7 MOV	0x130(%RSP),%R12

  (20) 0x405bff JNE	405a66

  (20) 0x405c05 JMP	405b20

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 26 - 98

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.23
Front-end cycles	3.25
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	3.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.23
Front-end cycles	3.25
P0 cycles	2.00
P1 cycles	3.00
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	13.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.81
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	13
nb uops	13
loop length	57
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	1.50	1.50	0.00	2.00	2.00	0.00
cycles	2.00	3.00	1.50	1.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.25
Dispatch	3.00
Data deps.	0.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

3% of peak load performance is reached (4.92 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 3.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 405a3d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%EDX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0x120(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%ECX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
JE 405c10 <main+0x2960>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %ESI,%EDX	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %EDX,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL 0xb8(%RSP),%EDX	1	0	1	0.50	0.50	0	0	3	1	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 405b45 <main+0x2895>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:26-98
Module	attention-icx-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26-33,98.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:26,31-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.25 to 1.00 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	13
nb uops	13
loop length	57
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	1.50	1.50	0.00	2.00	2.00	0.00
cycles	2.00	3.00	1.50	1.50	0.00	2.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.25
Dispatch	3.00
Data deps.	0.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	9%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

3% of peak load performance is reached (4.92 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 3.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 405a3d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
LEA 0x1(%RCX),%EDX	1	0	0.50	0	0	0.50	0	1	0.50	N/A
MOV 0x120(%RSP),%RSI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
ADD %RSI,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (12.5%)
CMP 0xac(%RSP),%ECX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	N/A
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0.25	N/A
JE 405c10 <main+0x2960>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %ESI,%EDX	1	0	1	0	0	0	0	3	1	scal (6.3%)
VPBROADCASTD %EDX,%YMM0	1	0	0	0	0	1	0	1	1	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL 0xb8(%RSP),%EDX	1	0	1	0.50	0.50	0	0	3	1	scal (6.3%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 405b45 <main+0x2895>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code