OV - attention-icx-skl512 - Loop 16

	Loop Id: 16	Module: attention-icx-skl512	Source: random.tcc:333-339 [...]	Coverage: 0.22%

0x403b00 MOV	%RDX,%RSI

0x403b03 SHR	$0x1e,%RSI

0x403b07 XOR	%RDX,%RSI

0x403b0a IMUL	$0x6c078965,%RSI,%RDX

0x403b11 ADD	%RCX,%RDX

0x403b14 INC	%RDX

0x403b17 MOV	%EDX,%ESI

0x403b19 MOV	%RSI,0x500(%RSP,%RCX,8)    [1]

0x403b21 MOV	%EDX,%ESI

0x403b23 SHR	$0x1e,%ESI

0x403b26 XOR	%RDX,%RSI

0x403b29 IMUL	$0x6c078965,%RSI,%RDX

0x403b30 ADD	%RCX,%RDX

0x403b33 ADD	$0x2,%RDX

0x403b37 MOV	%EDX,%ESI

0x403b39 MOV	%RSI,0x508(%RSP,%RCX,8)    [1]

0x403b41 MOV	%EDX,%ESI

0x403b43 SHR	$0x1e,%ESI

0x403b46 XOR	%RDX,%RSI

0x403b49 IMUL	$0x6c078965,%RSI,%RDX

0x403b50 ADD	%RCX,%RDX

0x403b53 ADD	$0x3,%RDX

0x403b57 MOV	%EDX,%ESI

0x403b59 MOV	%RSI,0x510(%RSP,%RCX,8)    [1]

0x403b61 MOV	%EDX,%ESI

0x403b63 SHR	$0x1e,%ESI

0x403b66 XOR	%RDX,%RSI

0x403b69 IMUL	$0x6c078965,%RSI,%RDX

0x403b70 ADD	%RCX,%RDX

0x403b73 ADD	$0x4,%RDX

0x403b77 MOV	%EDX,%ESI

0x403b79 MOV	%RSI,0x518(%RSP,%RCX,8)    [1]

0x403b81 MOV	%EDX,%ESI

0x403b83 SHR	$0x1e,%ESI

0x403b86 XOR	%RDX,%RSI

0x403b89 IMUL	$0x6c078965,%RSI,%RDX

0x403b90 ADD	%RCX,%RDX

0x403b93 ADD	$0x5,%RDX

0x403b97 MOV	%EDX,%ESI

0x403b99 MOV	%RSI,0x520(%RSP,%RCX,8)    [1]

0x403ba1 MOV	%EDX,%ESI

0x403ba3 SHR	$0x1e,%ESI

0x403ba6 XOR	%RDX,%RSI

0x403ba9 IMUL	$0x6c078965,%RSI,%RDX

0x403bb0 ADD	%RCX,%RDX

0x403bb3 ADD	$0x6,%RDX

0x403bb7 MOV	%EDX,%ESI

0x403bb9 MOV	%RSI,0x528(%RSP,%RCX,8)    [1]

0x403bc1 MOV	%EDX,%ESI

0x403bc3 SHR	$0x1e,%ESI

0x403bc6 XOR	%RDX,%RSI

0x403bc9 IMUL	$0x6c078965,%RSI,%RDX

0x403bd0 ADD	%RCX,%RDX

0x403bd3 ADD	$0x7,%RDX

0x403bd7 MOV	%EDX,%ESI

0x403bd9 MOV	%RSI,0x530(%RSP,%RCX,8)    [1]

0x403be1 MOV	%EDX,%ESI

0x403be3 SHR	$0x1e,%ESI

0x403be6 XOR	%RDX,%RSI

0x403be9 IMUL	$0x6c078965,%ESI,%EDX

0x403bef ADD	%ECX,%EDX

0x403bf1 ADD	$0x8,%EDX

0x403bf4 MOV	%RDX,0x538(%RSP,%RCX,8)    [1]

0x403bfc ADD	$0x8,%RCX

0x403c00 CMP	$0x268,%RCX

0x403c07 JNE	403b00

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.h: 585 - 585

--------------------------------------------------------------------------------

585: 	    __res %= __m;

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 333 - 339

--------------------------------------------------------------------------------

333:       for (size_t __i = 1; __i < state_size; ++__i)

334: 	{

335: 	  _UIntType __x = _M_x[__i - 1];

336: 	  __x ^= __x >> (__w - 2);

337: 	  __x *= __f;

338: 	  __x += __detail::__mod<_UIntType, __n>(__i);

339: 	  _M_x[__i] = __detail::__mod<_UIntType,

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	random.h:585-585,random.tcc:333-339
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.25
CQA cycles if no scalar integer	16.25
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	1.55
Front-end cycles	16.25
P0 cycles	10.50
P1 cycles	14.25
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	8.00
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.94
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.12
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	11.72
Vector-efficiency ratio add_sub	11.72
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.27

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.51
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	random.h:585-585,random.tcc:333-339
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.25
CQA cycles if no scalar integer	16.25
CQA cycles if FP arith vectorized	16.25
CQA cycles if fully vectorized	1.55
Front-end cycles	16.25
P0 cycles	10.50
P1 cycles	14.25
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	8.00
P5 cycles	10.50
P6 cycles	10.50
P7 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.94
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.12
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	11.72
Vector-efficiency ratio add_sub	11.72
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:333-339
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.h:585
/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:333-339

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.25 to 1.55 cycles (10.51x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	66
nb uops	65
loop length	269
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	10.50	10.50	2.67	2.67	8.00	10.50	10.50	2.67
cycles	10.50	14.25	2.67	2.67	8.00	10.50	10.50	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	16.25
Dispatch	14.25
Data deps.	0.00
Overall L1	16.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	11%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.25 cycles. At this rate:

6% of peak store performance is reached (3.94 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.25 to 14.25 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 403b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x1e,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
INC %RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x500(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x2,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x508(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x3,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x510(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x518(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x5,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x520(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x6,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x528(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x7,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x530(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
ADD $0x8,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV %RDX,0x538(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD $0x8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0x268,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 403b00 <main+0x850>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	random.tcc:333-339
Module	attention-icx-skl512

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.h:585
/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:333-339

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	66
nb uops	65
loop length	269
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	16.25 cycles
front end	16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	10.50	10.50	2.67	2.67	8.00	10.50	10.50	2.67
cycles	10.50	14.25	2.67	2.67	8.00	10.50	10.50	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	16.25
Dispatch	14.25
Data deps.	0.00
Overall L1	16.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	11%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.25 cycles. At this rate:

6% of peak store performance is reached (3.94 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 403b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0x1e,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
INC %RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x500(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x2,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x508(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x3,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x510(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x4,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x518(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x5,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x520(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x6,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x528(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%RSI,%RDX	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD $0x7,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,0x530(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SHR $0x1e,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
IMUL $0x6c078965,%ESI,%EDX	1	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
ADD $0x8,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV %RDX,0x538(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
ADD $0x8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0x268,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 403b00 <main+0x850>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code