OV - attention-icx-skl512 - Function _intel_fast

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x406bf0 ENDBR64

0x406bf4 MOV	0xe77d(%RIP),%RAX

0x406bfb TEST	%RAX,%RAX

0x406bfe JE	406c10

0x406c04 JMP	%RAX

0x406c06 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run run_0

Source file and lines
Module	attention-icx-skl512

gain
potential
hint
expert

Vectorization

Your function is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	5
nb uops	4
loop length	22
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	0.50	0.50	0.50	0.00	0.50	1.00	0.00
cycles	1.00	0.50	0.50	0.50	0.00	0.50	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.00
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.00 cycles. At this rate:

6% of peak load performance is reached (8.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.50 cycles (2.00x speedup).

ASM code

In the binary file, the address of the function is: 406bf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
ENDBR64												N/A
MOV 0xe77d(%RIP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %RAX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406c10 <__real_memset_impl_setup>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP %RAX	1	0	0	0	0	0	0	1	0	0	2	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.07% of application time for run run_0

Source file and lines
Module	attention-icx-skl512

gain
potential
hint
expert

Vectorization

Your function is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	5
nb uops	4
loop length	22
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	0.50	0.50	0.50	0.00	0.50	1.00	0.00
cycles	1.00	0.50	0.50	0.50	0.00	0.50	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.00
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.00 cycles. At this rate:

6% of peak load performance is reached (8.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.50 cycles (2.00x speedup).

ASM code

In the binary file, the address of the function is: 406bf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
ENDBR64												N/A
MOV 0xe77d(%RIP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %RAX,%RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406c10 <__real_memset_impl_setup>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP %RAX	1	0	0	0	0	0	0	1	0	0	2	N/A

Name	Coverage (%)	Time (s)
○_intel_fast_memset	0.07	0.01

Report Configuration

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code