OV - attention-icx-skl512 - Function __svml_expf16

	Function: __svml_expf16_z0	Module: attention-icx-skl512	Source: :0-0	Coverage (incl. loops): 0.29% \| (excl. loops): 0.29%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4069f0 ENDBR64

0x4069f4 VMOVUPS	0xb4c2(%RIP),%ZMM1

0x4069fe VMOVUPS	0xb4f8(%RIP),%ZMM2

0x406a08 VMOVUPS	0xb3ae(%RIP),%ZMM3

0x406a12 VFMADD213PS	{rz-sae},%ZMM2,%ZMM0,%ZMM1

0x406a18 VPERMT2PS	0xb3de(%RIP),%ZMM1,%ZMM3

0x406a22 VPSRLD	$0x5,%ZMM1,%ZMM4

0x406a29 VMOVUPS	0xb40d(%RIP),%ZMM5

0x406a33 VPERMT2PS	0xb443(%RIP),%ZMM4,%ZMM5

0x406a3d VMOVUPS	0xb4f9(%RIP),%ZMM4

0x406a47 VMOVUPS	0xb52f(%RIP),%ZMM6

0x406a51 VMOVUPS	0xb565(%RIP),%ZMM7

0x406a5b VCMPPS	$0x4,0xb6da(%RIP),%ZMM0,%K1

0x406a66 VMULPS	{rn-sae},%ZMM3,%ZMM5,%ZMM5{%K1}

0x406a6c VSUBPS	{rn-sae},%ZMM2,%ZMM1,%ZMM1

0x406a72 VFNMADD213PS	{rn-sae},%ZMM0,%ZMM1,%ZMM4

0x406a78 VFNMADD231PS	{rn-sae},%ZMM6,%ZMM1,%ZMM4

0x406a7e VRANGEPS	$0x2,{sae},%ZMM7,%ZMM4,%ZMM0

0x406a85 VFMADD132PS	{rn-sae},%ZMM5,%ZMM5,%ZMM0

0x406a8b VSCALEFPS	{rn-sae},%ZMM1,%ZMM0,%ZMM0

0x406a91 RET

0x406a92 NOPW	%CS:(%RAX,%RAX,1)

0x406a9c NOPL	(%RAX)

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.29% of application time for run run_0

Source file and lines
Module	attention-icx-skl512

gain
potential
hint
expert

Vectorization

Your function is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.25 cycles (1.14x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.09x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPS: 1 occurrences►

Vector unaligned load/store instructions

Detected 7 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 7 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

9 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 160 FP arithmetical operations:

80: addition or subtraction (64 inside FMA instructions)
80: multiply (64 inside FMA instructions)

The binary function is loading 640 bytes (160 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	21
loop length	162
used x86 registers	0
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	0.00	5.00	5.00	0.00	6.00	1.00	1.00
cycles	6.00	3.00	5.00	5.00	0.00	6.00	1.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

83% of peak load performance is reached (106.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4069f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
ENDBR64												N/A
VMOVUPS 0xb4c2(%RIP),%ZMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb4f8(%RIP),%ZMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb3ae(%RIP),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VFMADD213PS {rz-sae},%ZMM2,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VPERMT2PS 0xb3de(%RIP),%ZMM1,%ZMM3	1	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VPSRLD $0x5,%ZMM1,%ZMM4	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VMOVUPS 0xb40d(%RIP),%ZMM5	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VPERMT2PS 0xb443(%RIP),%ZMM4,%ZMM5	1	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VMOVUPS 0xb4f9(%RIP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb52f(%RIP),%ZMM6	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb565(%RIP),%ZMM7	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VCMPPS $0x4,0xb6da(%RIP),%ZMM0,%K1	2	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VMULPS {rn-sae},%ZMM3,%ZMM5,%ZMM5{%K1}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VSUBPS {rn-sae},%ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD213PS {rn-sae},%ZMM0,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PS {rn-sae},%ZMM6,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VRANGEPS $0x2,{sae},%ZMM7,%ZMM4,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PS {rn-sae},%ZMM5,%ZMM5,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VSCALEFPS {rn-sae},%ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.29% of application time for run run_0

Source file and lines
Module	attention-icx-skl512

gain
potential
hint
expert

Vectorization

Your function is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your function is irregular or mixes elements of different sizes.

Workaround

If your function is irregular, try to remove or hoist conditional structures out of your function. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 64 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCMPPS: 1 occurrences►

Vector unaligned load/store instructions

Detected 7 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 7 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

9 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 160 FP arithmetical operations:

80: addition or subtraction (64 inside FMA instructions)
80: multiply (64 inside FMA instructions)

The binary function is loading 640 bytes (160 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	21
loop length	162
used x86 registers	0
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	8
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	0.00	5.00	5.00	0.00	6.00	1.00	1.00
cycles	6.00	3.00	5.00	5.00	0.00	6.00	1.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

83% of peak load performance is reached (106.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4069f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
ENDBR64												N/A
VMOVUPS 0xb4c2(%RIP),%ZMM1	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb4f8(%RIP),%ZMM2	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb3ae(%RIP),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VFMADD213PS {rz-sae},%ZMM2,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VPERMT2PS 0xb3de(%RIP),%ZMM1,%ZMM3	1	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VPSRLD $0x5,%ZMM1,%ZMM4	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VMOVUPS 0xb40d(%RIP),%ZMM5	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VPERMT2PS 0xb443(%RIP),%ZMM4,%ZMM5	1	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VMOVUPS 0xb4f9(%RIP),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb52f(%RIP),%ZMM6	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VMOVUPS 0xb565(%RIP),%ZMM7	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (100.0%)
VCMPPS $0x4,0xb6da(%RIP),%ZMM0,%K1	2	0	0	0.50	0.50	0	1	0	0	3	1	vect (100.0%)
VMULPS {rn-sae},%ZMM3,%ZMM5,%ZMM5{%K1}	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VSUBPS {rn-sae},%ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD213PS {rn-sae},%ZMM0,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFNMADD231PS {rn-sae},%ZMM6,%ZMM1,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VRANGEPS $0x2,{sae},%ZMM7,%ZMM4,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VFMADD132PS {rn-sae},%ZMM5,%ZMM5,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
VSCALEFPS {rn-sae},%ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	4	0.50	vect (100.0%)
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A

Name	Coverage (%)	Time (s)
○__svml_expf16_z0	0.29	0.04

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code