| Loop Id: 56 | Module: attention-icx-skl256 | Source: random.tcc:404-3558 [...] | Coverage: 0.07% |
|---|
| Loop Id: 56 | Module: attention-icx-skl256 | Source: random.tcc:404-3558 [...] | Coverage: 0.07% |
|---|
0x403f50 MOV 0x2d8(%RSP,%RDX,8),%RSI |
0x403f58 INC %RDX |
0x403f5b MOV %RSI,%RDI |
0x403f5e SHR $0xb,%RDI |
0x403f62 MOV %EDI,%EDI |
0x403f64 XOR %RSI,%RDI |
0x403f67 MOV %EDI,%ESI |
0x403f69 SAL $0x7,%ESI |
0x403f6c AND $-0x62d3a980,%ESI |
0x403f72 XOR %RDI,%RSI |
0x403f75 MOV %ESI,%EDI |
0x403f77 SAL $0xf,%EDI |
0x403f7a AND $-0x103a0000,%EDI |
0x403f80 XOR %RSI,%RDI |
0x403f83 MOV %RDI,%RSI |
0x403f86 SHR $0x12,%RSI |
0x403f8a XOR %EDI,%ESI |
0x403f8c VCVTUSI2SS %ESI,%XMM25,%XMM0 |
0x403f92 VMULSS %XMM0,%XMM11,%XMM0 |
0x403f96 VUCOMISS %XMM12,%XMM0 |
0x403f9b JB 404170 |
0x403fa1 CMP $0x270,%RDX |
0x403fa8 JB 403f50 |
0x403faa XOR %EDX,%EDX |
0x403fac NOPL (%RAX) |
(57) 0x403fb0 VMOVDQU 0x2e0(%RSP,%RDX,1),%YMM0 |
(57) 0x403fb9 VPSRLQ $0x1,%YMM0,%YMM1 |
(57) 0x403fbe VPAND %YMM3,%YMM1,%YMM1 |
(57) 0x403fc2 VPBROADCASTQ %RAX,%YMM2 |
(57) 0x403fc8 VPBLENDD $-0x40,%YMM2,%YMM0,%YMM2 |
(57) 0x403fce VPSRLQ $0x1,%YMM2,%YMM2 |
(57) 0x403fd3 VPERMQ $-0x6d,%YMM2,%YMM2 |
(57) 0x403fd9 VPAND %YMM4,%YMM2,%YMM2 |
(57) 0x403fdd VPTERNLOGQ $0x56,0xf40(%RSP,%RDX,1),%YMM1,%YMM2 |
(57) 0x403fe6 VPTESTMQ %YMM5,%YMM0,%K1 |
(57) 0x403fec VPXORQ %YMM6,%YMM2,%YMM2{%K1} |
(57) 0x403ff2 VMOVDQU %YMM2,0x2d8(%RSP,%RDX,1) |
(57) 0x403ffb MOV 0x2f8(%RSP,%RDX,1),%RAX |
(57) 0x404003 ADD $0x20,%RDX |
(57) 0x404007 CMP $0x700,%RDX |
(57) 0x40400e JNE 403fb0 |
0x404010 MOV 0x9e8(%RSP),%RDX |
0x404018 VMOVDQU 0x9e0(%RSP),%XMM1 |
0x404021 VPSRLQ $0x1,%XMM1,%XMM2 |
0x404026 VPAND %XMM7,%XMM2,%XMM2 |
0x40402a VEXTRACTI128 $0x1,%YMM0,%XMM0 |
0x404030 VPALIGNR $0x8,%XMM0,%XMM1,%XMM0 |
0x404036 VPSRLQ $0x1,%XMM0,%XMM0 |
0x40403b VPAND %XMM0,%XMM8,%XMM0 |
0x40403f VPTERNLOGQ $0x56,0x1640(%RSP),%XMM2,%XMM0 |
0x40404b VPTESTMQ %XMM9,%XMM1,%K1 |
0x404051 VPXORQ %XMM10,%XMM0,%XMM0{%K1} |
0x404057 VMOVDQU %XMM0,0x9d8(%RSP) |
0x404060 MOV 0x9f0(%RSP),%RAX |
0x404068 MOV %EAX,%ESI |
0x40406a SHR $0x1,%ESI |
0x40406c AND $0x3fffffff,%ESI |
0x404072 SHR $0x1,%RDX |
0x404075 AND $-0x40000000,%RDX |
0x40407c OR %RSI,%RDX |
0x40407f XOR 0x1650(%RSP),%RDX |
0x404087 MOV %EAX,%ESI |
0x404089 AND $0x1,%ESI |
0x40408c NEG %ESI |
0x40408e AND $-0x66f74f21,%ESI |
0x404094 XOR %RDX,%RSI |
0x404097 MOV %RSI,0x9e8(%RSP) |
0x40409f XOR %EDX,%EDX |
0x4040a1 NOPW %CS:(%RAX,%RAX,1) |
(58) 0x4040b0 VMOVDQU 0x9f8(%RSP,%RDX,1),%YMM0 |
(58) 0x4040b9 VPSRLQ $0x1,%YMM0,%YMM1 |
(58) 0x4040be VPAND %YMM3,%YMM1,%YMM1 |
(58) 0x4040c2 VPBROADCASTQ %RAX,%YMM2 |
(58) 0x4040c8 VPBLENDD $-0x40,%YMM2,%YMM0,%YMM2 |
(58) 0x4040ce VPSRLQ $0x1,%YMM2,%YMM2 |
(58) 0x4040d3 VPERMQ $-0x6d,%YMM2,%YMM2 |
(58) 0x4040d9 VPAND %YMM4,%YMM2,%YMM2 |
(58) 0x4040dd VPTERNLOGQ $0x56,0x2d8(%RSP,%RDX,1),%YMM1,%YMM2 |
(58) 0x4040e9 VPTESTMQ %YMM5,%YMM0,%K1 |
(58) 0x4040ef VPXORQ %YMM6,%YMM2,%YMM2{%K1} |
(58) 0x4040f5 VMOVDQU %YMM2,0x9f0(%RSP,%RDX,1) |
(58) 0x4040fe MOV 0xa10(%RSP,%RDX,1),%RAX |
(58) 0x404106 ADD $0x20,%RDX |
(58) 0x40410a CMP $0xc60,%RDX |
(58) 0x404111 JNE 4040b0 |
0x404113 MOV 0x1650(%RSP),%RDX |
0x40411b MOV $-0x80000000,%RAX |
0x404122 AND %RAX,%RDX |
0x404125 MOV 0x2d8(%RSP),%RAX |
0x40412d MOV %EAX,%ESI |
0x40412f AND $0x7ffffffe,%ESI |
0x404135 OR %RDX,%RSI |
0x404138 SHR $0x1,%RSI |
0x40413b XOR 0xf38(%RSP),%RSI |
0x404143 MOV %EAX,%EDX |
0x404145 AND $0x1,%EDX |
0x404148 NEG %EDX |
0x40414a AND $-0x66f74f21,%EDX |
0x404150 XOR %RSI,%RDX |
0x404153 MOV %RDX,0x1650(%RSP) |
0x40415b MOV $0x1,%EDX |
0x404160 MOV %RAX,%RSI |
0x404163 JMP 403f5b |
/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558 |
-------------------------------------------------------------------------------- |
404: for (size_t __k = 0; __k < (__n - __m); ++__k) |
405: { |
406: _UIntType __y = ((_M_x[__k] & __upper_mask) |
407: | (_M_x[__k + 1] & __lower_mask)); |
408: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
409: ^ ((__y & 0x01) ? __a : 0)); |
410: } |
411: |
412: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
413: { |
414: _UIntType __y = ((_M_x[__k] & __upper_mask) |
415: | (_M_x[__k + 1] & __lower_mask)); |
416: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
417: ^ ((__y & 0x01) ? __a : 0)); |
418: } |
419: |
420: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
421: | (_M_x[0] & __lower_mask)); |
422: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
423: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
458: if (_M_p >= state_size) |
459: _M_gen_rand(); |
460: |
461: // Calculate o(x(i)). |
462: result_type __z = _M_x[_M_p++]; |
463: __z ^= (__z >> __u) & __d; |
464: __z ^= (__z << __s) & __b; |
465: __z ^= (__z << __t) & __c; |
466: __z ^= (__z >> __l); |
[...] |
3557: const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd); |
3558: if (__ret < _RealT(1.0)) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl256 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.69 |
| CQA speedup if FP arith vectorized | 2.20 |
| CQA speedup if fully vectorized | 11.31 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.44 |
| Bottlenecks | |
| Function | main |
| Source | random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 11.75 |
| CQA cycles if no scalar integer | 4.38 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 1.04 |
| Front-end cycles | 11.75 |
| P0 cycles | 8.17 |
| P1 cycles | 8.13 |
| P2 cycles | 2.25 |
| P3 cycles | 2.25 |
| P4 cycles | 1.50 |
| P5 cycles | 8.08 |
| P6 cycles | 8.13 |
| P7 cycles | 1.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 46.00 |
| Nb uops | 47.00 |
| Nb loads | 4.50 |
| Nb stores | 1.50 |
| Nb stack references | 4.00 |
| FLOP/cycle | 0.09 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 3.85 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 44.00 |
| Bytes stored | 16.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 11.11 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 33.33 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 10.00 |
| Vector-efficiency ratio all | 10.69 |
| Vector-efficiency ratio load | 16.67 |
| Vector-efficiency ratio store | 16.67 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 10.43 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.63 |
| CQA speedup if FP arith vectorized | 2.19 |
| CQA speedup if fully vectorized | 10.62 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.47 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 17.75 |
| CQA cycles if no scalar integer | 6.75 |
| CQA cycles if FP arith vectorized | 8.10 |
| CQA cycles if fully vectorized | 1.67 |
| Front-end cycles | 17.75 |
| P0 cycles | 12.08 |
| P1 cycles | 12.00 |
| P2 cycles | 4.00 |
| P3 cycles | 4.00 |
| P4 cycles | 3.00 |
| P5 cycles | 11.92 |
| P6 cycles | 12.00 |
| P7 cycles | 3.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 69.00 |
| Nb uops | 71.00 |
| Nb loads | 8.00 |
| Nb stores | 3.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 0.06 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.31 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 80.00 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 22.22 |
| Vectorization ratio load | 66.67 |
| Vectorization ratio store | 33.33 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 20.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 20.83 |
| Vector-efficiency ratio store | 16.67 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.03 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.88 |
| CQA speedup if FP arith vectorized | 2.24 |
| CQA speedup if fully vectorized | 14.15 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.35 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:407-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.56 |
| CQA cycles if fully vectorized | 0.41 |
| Front-end cycles | 5.75 |
| P0 cycles | 4.25 |
| P1 cycles | 4.25 |
| P2 cycles | 0.50 |
| P3 cycles | 0.50 |
| P4 cycles | 0.00 |
| P5 cycles | 4.25 |
| P6 cycles | 4.25 |
| P7 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | 1.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.17 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 1.39 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 8.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 8.88 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 8.82 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-icx-skl256 |
| nb instructions | 46 |
| nb uops | 47 |
| loop length | 210 |
| used x86 registers | 4.50 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 0.50 |
| used zmm registers | 0 |
| nb stack references | 4 |
| micro-operation queue | 11.75 cycles |
| front end | 11.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.17 | 8.13 | 2.25 | 2.25 | 1.50 | 8.08 | 8.13 | 1.50 |
| cycles | 8.17 | 8.13 | 2.25 | 2.25 | 1.50 | 8.08 | 8.13 | 1.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 11.75 |
| Dispatch | 8.17 |
| Data deps. | 0.00 |
| Overall L1 | 11.75 |
| all | 11% |
| load | 33% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 11% |
| load | 33% |
| store | 33% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| all | 10% |
| load | 16% |
| store | 16% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 6% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 10% |
| load | 16% |
| store | 16% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-icx-skl256 |
| nb instructions | 69 |
| nb uops | 71 |
| loop length | 330 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 10 |
| used ymm registers | 1 |
| used zmm registers | 0 |
| nb stack references | 8 |
| micro-operation queue | 17.75 cycles |
| front end | 17.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 12.08 | 12.00 | 4.00 | 4.00 | 3.00 | 11.92 | 12.00 | 3.00 |
| cycles | 12.08 | 12.00 | 4.00 | 4.00 | 3.00 | 11.92 | 12.00 | 3.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 17.75 |
| Dispatch | 12.08 |
| Data deps. | 0.00 |
| Overall L1 | 17.75 |
| all | 23% |
| load | 66% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 20% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 22% |
| load | 66% |
| store | 33% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 12% |
| load | 20% |
| store | 16% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 6% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 12% |
| load | 20% |
| store | 16% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %EDI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| SAL $0x7,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (6.3%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RDI,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %ESI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| SAL $0xf,%EDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (6.3%) |
| AND $-0x103a0000,%EDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %EDI,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| VCVTUSI2SS %ESI,%XMM25,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS %XMM0,%XMM11,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VUCOMISS %XMM12,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JB 404170 <main+0x1050> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMP $0x270,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JB 403f50 <main+0xe30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV 0x9e8(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| VMOVDQU 0x9e0(%RSP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (25.0%) |
| VPSRLQ $0x1,%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VPAND %XMM7,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (25.0%) |
| VEXTRACTI128 $0x1,%YMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VPALIGNR $0x8,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | scal (12.5%) |
| VPSRLQ $0x1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VPAND %XMM0,%XMM8,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (25.0%) |
| VPTERNLOGQ $0x56,0x1640(%RSP),%XMM2,%XMM0 | 2 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| VPTESTMQ %XMM9,%XMM1,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VPXORQ %XMM10,%XMM0,%XMM0{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (25.0%) |
| VMOVDQU %XMM0,0x9d8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 4 | 1 | vect (25.0%) |
| MOV 0x9f0(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| SHR $0x1,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (6.3%) |
| AND $0x3fffffff,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| SHR $0x1,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | N/A |
| AND $-0x40000000,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| OR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| XOR 0x1650(%RSP),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | N/A |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| AND $0x1,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| NEG %ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| AND $-0x66f74f21,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RSI,0x9e8(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| MOV 0x1650(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV $-0x80000000,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| AND %RAX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV 0x2d8(%RSP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | N/A |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| AND $0x7ffffffe,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| OR %RDX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| SHR $0x1,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR 0xf38(%RSP),%RSI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %EAX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| AND $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| NEG %EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| AND $-0x66f74f21,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| XOR %RSI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RDX,0x1650(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | scal (12.5%) |
| MOV $0x1,%EDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| JMP 403f5b <main+0xe3b> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 | N/A |
| Function | main |
| Source file and lines | random.tcc:404-3558 |
| Module | attention-icx-skl256 |
| nb instructions | 23 |
| nb uops | 23 |
| loop length | 90 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.75 cycles |
| front end | 5.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.25 | 4.25 | 0.50 | 0.50 | 0.00 | 4.25 | 4.25 | 0.00 |
| cycles | 4.25 | 4.25 | 0.50 | 0.50 | 0.00 | 4.25 | 4.25 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 5.75 |
| Dispatch | 4.25 |
| Data deps. | 0.00 |
| Overall L1 | 5.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 9% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 6% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| all | 8% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 8% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x2d8(%RSP,%RDX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 | scal (12.5%) |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0xb,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %EDI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| SAL $0x7,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (6.3%) |
| AND $-0x62d3a980,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RDI,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %ESI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (6.3%) |
| SAL $0xf,%EDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (6.3%) |
| AND $-0x103a0000,%EDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| XOR %RSI,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (12.5%) |
| MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| SHR $0x12,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %EDI,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| VCVTUSI2SS %ESI,%XMM25,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 6 | 1 | scal (6.3%) |
| VMULSS %XMM0,%XMM11,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VUCOMISS %XMM12,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (6.3%) |
| JB 404170 <main+0x1050> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| CMP $0x270,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JB 403f50 <main+0xe30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
