OV - attention-icx-skl256 - Loop 49

	Loop Id: 49	Module: attention-icx-skl256	Source: random.tcc:404-3558 [...]	Coverage: 0.15%

0x403f10 MOV	0xf0(%RSP),%RSI

0x403f18 VMOVSS	%XMM0,(%RSI,%RCX,4)

0x403f1d INC	%RCX

0x403f20 CMP	%R8,%RCX

0x403f23 JE	404630

0x403f29 VPBROADCASTQ	0xa24e(%RIP),%YMM3

0x403f32 VPBROADCASTQ	0xa24d(%RIP),%YMM4

0x403f3b VPBROADCASTQ	0xa24c(%RIP),%YMM5

0x403f44 VPBROADCASTQ	0xa24b(%RIP),%YMM6

0x403f4d JMP	403fa1

  (56) 0x403f50 MOV	0x2d8(%RSP,%RDX,8),%RSI

  (56) 0x403f58 INC	%RDX

  (56) 0x403f5b MOV	%RSI,%RDI

  (56) 0x403f5e SHR	$0xb,%RDI

  (56) 0x403f62 MOV	%EDI,%EDI

  (56) 0x403f64 XOR	%RSI,%RDI

  (56) 0x403f67 MOV	%EDI,%ESI

  (56) 0x403f69 SAL	$0x7,%ESI

  (56) 0x403f6c AND	$-0x62d3a980,%ESI

  (56) 0x403f72 XOR	%RDI,%RSI

  (56) 0x403f75 MOV	%ESI,%EDI

  (56) 0x403f77 SAL	$0xf,%EDI

  (56) 0x403f7a AND	$-0x103a0000,%EDI

  (56) 0x403f80 XOR	%RSI,%RDI

  (56) 0x403f83 MOV	%RDI,%RSI

  (56) 0x403f86 SHR	$0x12,%RSI

  (56) 0x403f8a XOR	%EDI,%ESI

  (56) 0x403f8c VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (56) 0x403f92 VMULSS	%XMM0,%XMM11,%XMM0

  (56) 0x403f96 VUCOMISS	%XMM12,%XMM0

  (56) 0x403f9b JB	404170

  (56) 0x403fa1 CMP	$0x270,%RDX

  (56) 0x403fa8 JB	403f50

  (56) 0x403faa XOR	%EDX,%EDX

  (56) 0x403fac NOPL	(%RAX)

    (57) 0x403fb0 VMOVDQU	0x2e0(%RSP,%RDX,1),%YMM0

    (57) 0x403fb9 VPSRLQ	$0x1,%YMM0,%YMM1

    (57) 0x403fbe VPAND	%YMM3,%YMM1,%YMM1

    (57) 0x403fc2 VPBROADCASTQ	%RAX,%YMM2

    (57) 0x403fc8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (57) 0x403fce VPSRLQ	$0x1,%YMM2,%YMM2

    (57) 0x403fd3 VPERMQ	$-0x6d,%YMM2,%YMM2

    (57) 0x403fd9 VPAND	%YMM4,%YMM2,%YMM2

    (57) 0x403fdd VPTERNLOGQ	$0x56,0xf40(%RSP,%RDX,1),%YMM1,%YMM2

    (57) 0x403fe6 VPTESTMQ	%YMM5,%YMM0,%K1

    (57) 0x403fec VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (57) 0x403ff2 VMOVDQU	%YMM2,0x2d8(%RSP,%RDX,1)

    (57) 0x403ffb MOV	0x2f8(%RSP,%RDX,1),%RAX

    (57) 0x404003 ADD	$0x20,%RDX

    (57) 0x404007 CMP	$0x700,%RDX

    (57) 0x40400e JNE	403fb0

  (56) 0x404010 MOV	0x9e8(%RSP),%RDX

  (56) 0x404018 VMOVDQU	0x9e0(%RSP),%XMM1

  (56) 0x404021 VPSRLQ	$0x1,%XMM1,%XMM2

  (56) 0x404026 VPAND	%XMM7,%XMM2,%XMM2

  (56) 0x40402a VEXTRACTI128	$0x1,%YMM0,%XMM0

  (56) 0x404030 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (56) 0x404036 VPSRLQ	$0x1,%XMM0,%XMM0

  (56) 0x40403b VPAND	%XMM0,%XMM8,%XMM0

  (56) 0x40403f VPTERNLOGQ	$0x56,0x1640(%RSP),%XMM2,%XMM0

  (56) 0x40404b VPTESTMQ	%XMM9,%XMM1,%K1

  (56) 0x404051 VPXORQ	%XMM10,%XMM0,%XMM0{%K1}

  (56) 0x404057 VMOVDQU	%XMM0,0x9d8(%RSP)

  (56) 0x404060 MOV	0x9f0(%RSP),%RAX

  (56) 0x404068 MOV	%EAX,%ESI

  (56) 0x40406a SHR	$0x1,%ESI

  (56) 0x40406c AND	$0x3fffffff,%ESI

  (56) 0x404072 SHR	$0x1,%RDX

  (56) 0x404075 AND	$-0x40000000,%RDX

  (56) 0x40407c OR	%RSI,%RDX

  (56) 0x40407f XOR	0x1650(%RSP),%RDX

  (56) 0x404087 MOV	%EAX,%ESI

  (56) 0x404089 AND	$0x1,%ESI

  (56) 0x40408c NEG	%ESI

  (56) 0x40408e AND	$-0x66f74f21,%ESI

  (56) 0x404094 XOR	%RDX,%RSI

  (56) 0x404097 MOV	%RSI,0x9e8(%RSP)

  (56) 0x40409f XOR	%EDX,%EDX

  (56) 0x4040a1 NOPW	%CS:(%RAX,%RAX,1)

    (58) 0x4040b0 VMOVDQU	0x9f8(%RSP,%RDX,1),%YMM0

    (58) 0x4040b9 VPSRLQ	$0x1,%YMM0,%YMM1

    (58) 0x4040be VPAND	%YMM3,%YMM1,%YMM1

    (58) 0x4040c2 VPBROADCASTQ	%RAX,%YMM2

    (58) 0x4040c8 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (58) 0x4040ce VPSRLQ	$0x1,%YMM2,%YMM2

    (58) 0x4040d3 VPERMQ	$-0x6d,%YMM2,%YMM2

    (58) 0x4040d9 VPAND	%YMM4,%YMM2,%YMM2

    (58) 0x4040dd VPTERNLOGQ	$0x56,0x2d8(%RSP,%RDX,1),%YMM1,%YMM2

    (58) 0x4040e9 VPTESTMQ	%YMM5,%YMM0,%K1

    (58) 0x4040ef VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (58) 0x4040f5 VMOVDQU	%YMM2,0x9f0(%RSP,%RDX,1)

    (58) 0x4040fe MOV	0xa10(%RSP,%RDX,1),%RAX

    (58) 0x404106 ADD	$0x20,%RDX

    (58) 0x40410a CMP	$0xc60,%RDX

    (58) 0x404111 JNE	4040b0

  (56) 0x404113 MOV	0x1650(%RSP),%RDX

  (56) 0x40411b MOV	$-0x80000000,%RAX

  (56) 0x404122 AND	%RAX,%RDX

  (56) 0x404125 MOV	0x2d8(%RSP),%RAX

  (56) 0x40412d MOV	%EAX,%ESI

  (56) 0x40412f AND	$0x7ffffffe,%ESI

  (56) 0x404135 OR	%RDX,%RSI

  (56) 0x404138 SHR	$0x1,%RSI

  (56) 0x40413b XOR	0xf38(%RSP),%RSI

  (56) 0x404143 MOV	%EAX,%EDX

  (56) 0x404145 AND	$0x1,%EDX

  (56) 0x404148 NEG	%EDX

  (56) 0x40414a AND	$-0x66f74f21,%EDX

  (56) 0x404150 XOR	%RSI,%RDX

  (56) 0x404153 MOV	%RDX,0x1650(%RSP)

  (56) 0x40415b MOV	$0x1,%EDX

  (56) 0x404160 MOV	%RAX,%RSI

  (56) 0x404163 JMP	403f5b

0x404170 MOV	0x100(%RSP),%RSI

0x404178 VMOVSS	%XMM0,(%RSI,%RCX,4)

0x40417d VPBROADCASTQ	0x9ffa(%RIP),%YMM3

0x404186 VPBROADCASTQ	0x9ff9(%RIP),%YMM4

0x40418f VPBROADCASTQ	0x9ff8(%RIP),%YMM5

0x404198 VPBROADCASTQ	0x9ff7(%RIP),%YMM6

0x4041a1 JMP	404204

  (53) 0x4041b0 MOV	0x2d8(%RSP,%RDX,8),%RSI

  (53) 0x4041b8 INC	%RDX

  (53) 0x4041bb MOV	%RSI,%RDI

  (53) 0x4041be SHR	$0xb,%RDI

  (53) 0x4041c2 MOV	%EDI,%EDI

  (53) 0x4041c4 XOR	%RSI,%RDI

  (53) 0x4041c7 MOV	%EDI,%ESI

  (53) 0x4041c9 SAL	$0x7,%ESI

  (53) 0x4041cc AND	$-0x62d3a980,%ESI

  (53) 0x4041d2 XOR	%RDI,%RSI

  (53) 0x4041d5 MOV	%ESI,%EDI

  (53) 0x4041d7 SAL	$0xf,%EDI

  (53) 0x4041da AND	$-0x103a0000,%EDI

  (53) 0x4041e0 XOR	%RSI,%RDI

  (53) 0x4041e3 MOV	%RDI,%RSI

  (53) 0x4041e6 SHR	$0x12,%RSI

  (53) 0x4041ea XOR	%EDI,%ESI

  (53) 0x4041ec VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (53) 0x4041f2 VMULSS	%XMM17,%XMM0,%XMM0

  (53) 0x4041f8 VUCOMISS	%XMM18,%XMM0

  (53) 0x4041fe JB	4043d0

  (53) 0x404204 CMP	$0x270,%RDX

  (53) 0x40420b JB	4041b0

  (53) 0x40420d XOR	%EDX,%EDX

  (53) 0x40420f NOP

    (54) 0x404210 VMOVDQU	0x2e0(%RSP,%RDX,1),%YMM0

    (54) 0x404219 VPSRLQ	$0x1,%YMM0,%YMM1

    (54) 0x40421e VPAND	%YMM3,%YMM1,%YMM1

    (54) 0x404222 VPBROADCASTQ	%RAX,%YMM2

    (54) 0x404228 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (54) 0x40422e VPSRLQ	$0x1,%YMM2,%YMM2

    (54) 0x404233 VPERMQ	$-0x6d,%YMM2,%YMM2

    (54) 0x404239 VPAND	%YMM4,%YMM2,%YMM2

    (54) 0x40423d VPTERNLOGQ	$0x56,0xf40(%RSP,%RDX,1),%YMM1,%YMM2

    (54) 0x404246 VPTESTMQ	%YMM5,%YMM0,%K1

    (54) 0x40424c VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (54) 0x404252 VMOVDQU	%YMM2,0x2d8(%RSP,%RDX,1)

    (54) 0x40425b MOV	0x2f8(%RSP,%RDX,1),%RAX

    (54) 0x404263 ADD	$0x20,%RDX

    (54) 0x404267 CMP	$0x700,%RDX

    (54) 0x40426e JNE	404210

  (53) 0x404270 MOV	0x9e8(%RSP),%RDX

  (53) 0x404278 VMOVDQU	0x9e0(%RSP),%XMM1

  (53) 0x404281 VPSRLQ	$0x1,%XMM1,%XMM2

  (53) 0x404286 VPAND	%XMM2,%XMM13,%XMM2

  (53) 0x40428a VEXTRACTI128	$0x1,%YMM0,%XMM0

  (53) 0x404290 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (53) 0x404296 VPSRLQ	$0x1,%XMM0,%XMM0

  (53) 0x40429b VPAND	%XMM0,%XMM14,%XMM0

  (53) 0x40429f VPTERNLOGQ	$0x56,0x1640(%RSP),%XMM2,%XMM0

  (53) 0x4042ab VPTESTMQ	%XMM15,%XMM1,%K1

  (53) 0x4042b1 VPXORQ	%XMM16,%XMM0,%XMM0{%K1}

  (53) 0x4042b7 VMOVDQU	%XMM0,0x9d8(%RSP)

  (53) 0x4042c0 MOV	0x9f0(%RSP),%RAX

  (53) 0x4042c8 MOV	%EAX,%ESI

  (53) 0x4042ca SHR	$0x1,%ESI

  (53) 0x4042cc AND	$0x3fffffff,%ESI

  (53) 0x4042d2 SHR	$0x1,%RDX

  (53) 0x4042d5 AND	$-0x40000000,%RDX

  (53) 0x4042dc OR	%RSI,%RDX

  (53) 0x4042df XOR	0x1650(%RSP),%RDX

  (53) 0x4042e7 MOV	%EAX,%ESI

  (53) 0x4042e9 AND	$0x1,%ESI

  (53) 0x4042ec NEG	%ESI

  (53) 0x4042ee AND	$-0x66f74f21,%ESI

  (53) 0x4042f4 XOR	%RDX,%RSI

  (53) 0x4042f7 MOV	%RSI,0x9e8(%RSP)

  (53) 0x4042ff XOR	%EDX,%EDX

  (53) 0x404301 NOPW	%CS:(%RAX,%RAX,1)

    (55) 0x404310 VMOVDQU	0x9f8(%RSP,%RDX,1),%YMM0

    (55) 0x404319 VPSRLQ	$0x1,%YMM0,%YMM1

    (55) 0x40431e VPAND	%YMM3,%YMM1,%YMM1

    (55) 0x404322 VPBROADCASTQ	%RAX,%YMM2

    (55) 0x404328 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (55) 0x40432e VPSRLQ	$0x1,%YMM2,%YMM2

    (55) 0x404333 VPERMQ	$-0x6d,%YMM2,%YMM2

    (55) 0x404339 VPAND	%YMM4,%YMM2,%YMM2

    (55) 0x40433d VPTERNLOGQ	$0x56,0x2d8(%RSP,%RDX,1),%YMM1,%YMM2

    (55) 0x404349 VPTESTMQ	%YMM5,%YMM0,%K1

    (55) 0x40434f VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (55) 0x404355 VMOVDQU	%YMM2,0x9f0(%RSP,%RDX,1)

    (55) 0x40435e MOV	0xa10(%RSP,%RDX,1),%RAX

    (55) 0x404366 ADD	$0x20,%RDX

    (55) 0x40436a CMP	$0xc60,%RDX

    (55) 0x404371 JNE	404310

  (53) 0x404373 MOV	0x1650(%RSP),%RDX

  (53) 0x40437b MOV	$-0x80000000,%RAX

  (53) 0x404382 AND	%RAX,%RDX

  (53) 0x404385 MOV	0x2d8(%RSP),%RAX

  (53) 0x40438d MOV	%EAX,%ESI

  (53) 0x40438f AND	$0x7ffffffe,%ESI

  (53) 0x404395 OR	%RDX,%RSI

  (53) 0x404398 SHR	$0x1,%RSI

  (53) 0x40439b XOR	0xf38(%RSP),%RSI

  (53) 0x4043a3 MOV	%EAX,%EDX

  (53) 0x4043a5 AND	$0x1,%EDX

  (53) 0x4043a8 NEG	%EDX

  (53) 0x4043aa AND	$-0x66f74f21,%EDX

  (53) 0x4043b0 XOR	%RSI,%RDX

  (53) 0x4043b3 MOV	%RDX,0x1650(%RSP)

  (53) 0x4043bb MOV	$0x1,%EDX

  (53) 0x4043c0 MOV	%RAX,%RSI

  (53) 0x4043c3 JMP	4041bb

0x4043d0 MOV	0xf8(%RSP),%RSI

0x4043d8 VMOVSS	%XMM0,(%RSI,%RCX,4)

0x4043dd VPBROADCASTQ	0x9d9a(%RIP),%YMM3

0x4043e6 VPBROADCASTQ	0x9d99(%RIP),%YMM4

0x4043ef VPBROADCASTQ	0x9d98(%RIP),%YMM5

0x4043f8 VPBROADCASTQ	0x9d97(%RIP),%YMM6

0x404401 JMP	404464

  (50) 0x404410 MOV	0x2d8(%RSP,%RDX,8),%RSI

  (50) 0x404418 INC	%RDX

  (50) 0x40441b MOV	%RSI,%RDI

  (50) 0x40441e SHR	$0xb,%RDI

  (50) 0x404422 MOV	%EDI,%EDI

  (50) 0x404424 XOR	%RSI,%RDI

  (50) 0x404427 MOV	%EDI,%ESI

  (50) 0x404429 SAL	$0x7,%ESI

  (50) 0x40442c AND	$-0x62d3a980,%ESI

  (50) 0x404432 XOR	%RDI,%RSI

  (50) 0x404435 MOV	%ESI,%EDI

  (50) 0x404437 SAL	$0xf,%EDI

  (50) 0x40443a AND	$-0x103a0000,%EDI

  (50) 0x404440 XOR	%RSI,%RDI

  (50) 0x404443 MOV	%RDI,%RSI

  (50) 0x404446 SHR	$0x12,%RSI

  (50) 0x40444a XOR	%EDI,%ESI

  (50) 0x40444c VCVTUSI2SS	%ESI,%XMM25,%XMM0

  (50) 0x404452 VMULSS	%XMM23,%XMM0,%XMM0

  (50) 0x404458 VUCOMISS	%XMM24,%XMM0

  (50) 0x40445e JB	403f10

  (50) 0x404464 CMP	$0x270,%RDX

  (50) 0x40446b JB	404410

  (50) 0x40446d XOR	%EDX,%EDX

  (50) 0x40446f NOP

    (51) 0x404470 VMOVDQU	0x2e0(%RSP,%RDX,1),%YMM0

    (51) 0x404479 VPSRLQ	$0x1,%YMM0,%YMM1

    (51) 0x40447e VPAND	%YMM3,%YMM1,%YMM1

    (51) 0x404482 VPBROADCASTQ	%RAX,%YMM2

    (51) 0x404488 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (51) 0x40448e VPSRLQ	$0x1,%YMM2,%YMM2

    (51) 0x404493 VPERMQ	$-0x6d,%YMM2,%YMM2

    (51) 0x404499 VPAND	%YMM4,%YMM2,%YMM2

    (51) 0x40449d VPTERNLOGQ	$0x56,0xf40(%RSP,%RDX,1),%YMM1,%YMM2

    (51) 0x4044a6 VPTESTMQ	%YMM5,%YMM0,%K1

    (51) 0x4044ac VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (51) 0x4044b2 VMOVDQU	%YMM2,0x2d8(%RSP,%RDX,1)

    (51) 0x4044bb MOV	0x2f8(%RSP,%RDX,1),%RAX

    (51) 0x4044c3 ADD	$0x20,%RDX

    (51) 0x4044c7 CMP	$0x700,%RDX

    (51) 0x4044ce JNE	404470

  (50) 0x4044d0 MOV	0x9e8(%RSP),%RDX

  (50) 0x4044d8 VMOVDQU	0x9e0(%RSP),%XMM1

  (50) 0x4044e1 VPSRLQ	$0x1,%XMM1,%XMM2

  (50) 0x4044e6 VPANDQ	%XMM19,%XMM2,%XMM2

  (50) 0x4044ec VEXTRACTI128	$0x1,%YMM0,%XMM0

  (50) 0x4044f2 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (50) 0x4044f8 VPSRLQ	$0x1,%XMM0,%XMM0

  (50) 0x4044fd VPANDQ	%XMM20,%XMM0,%XMM0

  (50) 0x404503 VPTERNLOGQ	$0x56,0x1640(%RSP),%XMM2,%XMM0

  (50) 0x40450f VPTESTMQ	%XMM21,%XMM1,%K1

  (50) 0x404515 VPXORQ	%XMM22,%XMM0,%XMM0{%K1}

  (50) 0x40451b VMOVDQU	%XMM0,0x9d8(%RSP)

  (50) 0x404524 MOV	0x9f0(%RSP),%RAX

  (50) 0x40452c MOV	%EAX,%ESI

  (50) 0x40452e SHR	$0x1,%ESI

  (50) 0x404530 AND	$0x3fffffff,%ESI

  (50) 0x404536 SHR	$0x1,%RDX

  (50) 0x404539 AND	$-0x40000000,%RDX

  (50) 0x404540 OR	%RSI,%RDX

  (50) 0x404543 XOR	0x1650(%RSP),%RDX

  (50) 0x40454b MOV	%EAX,%ESI

  (50) 0x40454d AND	$0x1,%ESI

  (50) 0x404550 NEG	%ESI

  (50) 0x404552 AND	$-0x66f74f21,%ESI

  (50) 0x404558 XOR	%RDX,%RSI

  (50) 0x40455b MOV	%RSI,0x9e8(%RSP)

  (50) 0x404563 XOR	%EDX,%EDX

  (50) 0x404565 NOPW	%CS:(%RAX,%RAX,1)

    (52) 0x404570 VMOVDQU	0x9f8(%RSP,%RDX,1),%YMM0

    (52) 0x404579 VPSRLQ	$0x1,%YMM0,%YMM1

    (52) 0x40457e VPAND	%YMM3,%YMM1,%YMM1

    (52) 0x404582 VPBROADCASTQ	%RAX,%YMM2

    (52) 0x404588 VPBLENDD	$-0x40,%YMM2,%YMM0,%YMM2

    (52) 0x40458e VPSRLQ	$0x1,%YMM2,%YMM2

    (52) 0x404593 VPERMQ	$-0x6d,%YMM2,%YMM2

    (52) 0x404599 VPAND	%YMM4,%YMM2,%YMM2

    (52) 0x40459d VPTERNLOGQ	$0x56,0x2d8(%RSP,%RDX,1),%YMM1,%YMM2

    (52) 0x4045a9 VPTESTMQ	%YMM5,%YMM0,%K1

    (52) 0x4045af VPXORQ	%YMM6,%YMM2,%YMM2{%K1}

    (52) 0x4045b5 VMOVDQU	%YMM2,0x9f0(%RSP,%RDX,1)

    (52) 0x4045be MOV	0xa10(%RSP,%RDX,1),%RAX

    (52) 0x4045c6 ADD	$0x20,%RDX

    (52) 0x4045ca CMP	$0xc60,%RDX

    (52) 0x4045d1 JNE	404570

  (50) 0x4045d3 MOV	0x1650(%RSP),%RDX

  (50) 0x4045db MOV	$-0x80000000,%RAX

  (50) 0x4045e2 AND	%RAX,%RDX

  (50) 0x4045e5 MOV	0x2d8(%RSP),%RAX

  (50) 0x4045ed MOV	%EAX,%ESI

  (50) 0x4045ef AND	$0x7ffffffe,%ESI

  (50) 0x4045f5 OR	%RDX,%RSI

  (50) 0x4045f8 SHR	$0x1,%RSI

  (50) 0x4045fb XOR	0xf38(%RSP),%RSI

  (50) 0x404603 MOV	%EAX,%EDX

  (50) 0x404605 AND	$0x1,%EDX

  (50) 0x404608 NEG	%EDX

  (50) 0x40460a AND	$-0x66f74f21,%EDX

  (50) 0x404610 XOR	%RSI,%RDX

  (50) 0x404613 MOV	%RDX,0x1650(%RSP)

  (50) 0x40461b MOV	$0x1,%EDX

  (50) 0x404620 MOV	%RAX,%RSI

  (50) 0x404623 JMP	40441b

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3,
Function	main
Source	random.tcc:422-422,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	0.84
Front-end cycles	6.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	15.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.60
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P2, P3,
Function	main
Source	random.tcc:422-422,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	0.84
Front-end cycles	6.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	3.00
P5 cycles	1.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	15.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.60
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	24
nb uops	24
loop length	165
used x86 registers	4
used mmx registers	0
used xmm registers	1
used ymm registers	4
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	7.50	7.50	3.00	1.00	3.00	3.00
cycles	1.00	1.00	7.50	7.50	3.00	1.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	7.50
Overall L1	7.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

12% of peak load performance is reached (16.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403f29

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xf0(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 404630 <main+0x1510>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0xa24e(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24d(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24c(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24b(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 403fa1 <main+0xe81>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x100(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9ffa(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff9(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff8(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff7(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404204 <main+0x10e4>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0xf8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9d9a(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d99(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d98(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d97(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404464 <main+0x1344>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	random.tcc:404-3558
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 6.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	24
nb uops	24
loop length	165
used x86 registers	4
used mmx registers	0
used xmm registers	1
used ymm registers	4
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.00	1.00	7.50	7.50	3.00	1.00	3.00	3.00
cycles	1.00	1.00	7.50	7.50	3.00	1.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	7.50
Overall L1	7.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

12% of peak load performance is reached (16.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403f29

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0xf0(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R8,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 404630 <main+0x1510>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0xa24e(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24d(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24c(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0xa24b(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 403fa1 <main+0xe81>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x100(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9ffa(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff9(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff8(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9ff7(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404204 <main+0x10e4>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0xf8(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RSI,%RCX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VPBROADCASTQ 0x9d9a(%RIP),%YMM3	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d99(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d98(%RIP),%YMM5	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x9d97(%RIP),%YMM6	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
JMP 404464 <main+0x1344>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code