OV - attention-icx-skl256 - Loop 45

	Loop Id: 45	Module: attention-icx-skl256	Source: attention_v2.cpp:30-31	Coverage: 9.94%

0x4048a0 LEA	(%RAX,%R8,1),%R9D

0x4048a4 VPBROADCASTD	%R9D,%XMM2

0x4048aa LEA	(%RBX,%R12,1),%R9

0x4048ae VXORPD	%XMM3,%XMM3,%XMM3

0x4048b2 VPCMPEQB	%XMM0,%XMM0,%K1

0x4048b8 VPBROADCASTD	%R8D,%XMM4

0x4048be VPADDD	%XMM7,%XMM2,%XMM2

0x4048c2 VPADDD	%XMM4,%XMM8,%XMM4

0x4048c6 VPMULLD	%XMM4,%XMM6,%XMM4

0x4048cb VPADDD	%XMM4,%XMM1,%XMM4

0x4048cf LEA	(%R11,%R12,1),%R10

0x4048d3 VPSUBD	%XMM9,%XMM4,%XMM4

0x4048d8 VPXOR	%XMM5,%XMM5,%XMM5

0x4048dc VGATHERDPS	(%R9,%XMM2,4),%XMM3{%K1}    [2]

0x4048e3 VPCMPEQB	%XMM0,%XMM0,%K1

0x4048e9 VGATHERDPS	(%R10,%XMM4,4),%XMM5{%K1}    [1]

0x4048f0 VCVTPS2PD	%XMM3,%YMM2

0x4048f4 VCVTPS2PD	%XMM5,%YMM3

0x4048f8 VFMADD231PD	%YMM3,%YMM2,%YMM0

0x4048fd ADD	$0x4,%R8

0x404901 CMP	%R15,%R8

0x404904 JB	4048a0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	7.00
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.46
Front-end cycles	7.00
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.67
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	28.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.14
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.57
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	87.50
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	80.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.25

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.17
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	7.00
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.46
Front-end cycles	7.00
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	0.00
P5 cycles	6.67
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	28.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.14
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.57
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	87.50
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	80.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is intermediate loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.25 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	28
loop length	102
used x86 registers	8
used mmx registers	0
used xmm registers	10
used ymm registers	3
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.67	6.67	4.00	4.00	0.00	6.67	2.00	0.00
cycles	6.67	6.67	4.00	4.00	0.00	6.67	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.00
Dispatch	6.67
Data deps.	4.00
Overall L1	7.00

Vectorization ratios

INT

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

Vector efficiency ratios

INT

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	29%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

3% of peak load performance is reached (4.57 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 6.67 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 4048a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA (%RAX,%R8,1),%R9D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPBROADCASTD %R9D,%XMM2	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
LEA (%RBX,%R12,1),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VPBROADCASTD %R8D,%XMM4	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %XMM7,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPADDD %XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPMULLD %XMM4,%XMM6,%XMM4	2	1	1	0	0	0	0	0	0	10	1	vect (25.0%)
VPADDD %XMM4,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
LEA (%R11,%R12,1),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %XMM9,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VGATHERDPS (%R9,%XMM2,4),%XMM3{%K1}	4	1	0	2	2	0	1	0	0	19	4	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VGATHERDPS (%R10,%XMM4,4),%XMM5{%K1}	4	1	0	2	2	0	1	0	0	19	4	vect (25.0%)
VCVTPS2PD %XMM3,%YMM2	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM5,%YMM3	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VFMADD231PD %YMM3,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JB 4048a0 <main+0x1780>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is intermediate loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.25 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 4 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
4: multiply (all inside FMA instructions)

The binary loop is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	28
loop length	102
used x86 registers	8
used mmx registers	0
used xmm registers	10
used ymm registers	3
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.67	6.67	4.00	4.00	0.00	6.67	2.00	0.00
cycles	6.67	6.67	4.00	4.00	0.00	6.67	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.00
Dispatch	6.67
Data deps.	4.00
Overall L1	7.00

Vectorization ratios

INT

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	87%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

Vector efficiency ratios

INT

all	21%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	29%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	24%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

3% of peak load performance is reached (4.57 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4048a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
LEA (%RAX,%R8,1),%R9D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPBROADCASTD %R9D,%XMM2	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
LEA (%RBX,%R12,1),%R9	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VPBROADCASTD %R8D,%XMM4	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %XMM7,%XMM2,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPADDD %XMM4,%XMM8,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPMULLD %XMM4,%XMM6,%XMM4	2	1	1	0	0	0	0	0	0	10	1	vect (25.0%)
VPADDD %XMM4,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
LEA (%R11,%R12,1),%R10	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VPSUBD %XMM9,%XMM4,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (25.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VGATHERDPS (%R9,%XMM2,4),%XMM3{%K1}	4	1	0	2	2	0	1	0	0	19	4	vect (25.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VGATHERDPS (%R10,%XMM4,4),%XMM5{%K1}	4	1	0	2	2	0	1	0	0	19	4	vect (25.0%)
VCVTPS2PD %XMM3,%YMM2	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM5,%YMM3	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VFMADD231PD %YMM3,%YMM2,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x4,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R15,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JB 4048a0 <main+0x1780>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code