OV - attention-icx-skl256 - Loop 39

	Loop Id: 39	Module: attention-icx-skl256	Source: attention_v2.cpp:237-238	Coverage: 0.15%

0x404c40 MOV	%R9D,%R11D

0x404c43 VMOVSS	-0x1c(%R8,%R10,1),%XMM0    [2]

0x404c4a VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404c50 LEA	(%RAX,%R9,1),%R11D

0x404c54 VMOVSS	-0x18(%R8,%R10,1),%XMM0    [2]

0x404c5b VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404c61 MOV	0x288(%RSP),%R11    [1]

0x404c69 ADD	%R9D,%R11D

0x404c6c VMOVSS	-0x14(%R8,%R10,1),%XMM0    [2]

0x404c73 VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404c79 MOV	0x280(%RSP),%R11    [1]

0x404c81 LEA	(%R11,%R9,1),%R11D

0x404c85 VMOVSS	-0x10(%R8,%R10,1),%XMM0    [2]

0x404c8c VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404c92 MOV	0x278(%RSP),%R11    [1]

0x404c9a LEA	(%R11,%R9,1),%R11D

0x404c9e VMOVSS	-0xc(%R8,%R10,1),%XMM0    [2]

0x404ca5 VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404cab LEA	(%RDI,%R9,1),%R11D

0x404caf VMOVSS	-0x8(%R8,%R10,1),%XMM0    [2]

0x404cb6 VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404cbc LEA	(%RDX,%R9,1),%R11D

0x404cc0 VMOVSS	-0x4(%R8,%R10,1),%XMM0    [2]

0x404cc7 VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404ccd VMOVSS	(%R8,%R10,1),%XMM0    [2]

0x404cd3 MOV	0x298(%RSP),%R11    [1]

0x404cdb ADD	%R9D,%R11D

0x404cde VMOVSS	%XMM0,(%RSI,%R11,4)    [3]

0x404ce4 ADD	$0x20,%R10

0x404ce8 ADD	%ECX,%R9D

0x404ceb CMP	%R10,0x290(%RSP)    [1]

0x404cf3 JNE	404c40

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 237 - 238

--------------------------------------------------------------------------------

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.50
Front-end cycles	7.75
P0 cycles	2.50
P1 cycles	3.50
P2 cycles	7.17
P3 cycles	6.83
P4 cycles	8.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	31.00
Nb loads	13.00
Nb stores	8.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.00
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P4,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	0.50
Front-end cycles	7.75
P0 cycles	2.50
P1 cycles	3.50
P2 cycles	7.17
P3 cycles	6.83
P4 cycles	8.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	31.00
Nb loads	13.00
Nb stores	8.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.00
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 0.50 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
nb uops	31
loop length	185
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	7.17	6.83	8.00	2.50	2.50	7.00
cycles	2.50	3.50	7.17	6.83	8.00	2.50	2.50	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.75
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (9.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS -0x1c(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RAX,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x18(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x288(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R9D,%R11D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS -0x14(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x280(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R11,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x10(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x278(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R11,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0xc(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RDI,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x8(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RDX,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x4(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVSS (%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV 0x298(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R9D,%R11D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x20,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %ECX,%R9D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R10,0x290(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 404c40 <main+0x1b20>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
nb uops	31
loop length	185
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	7.17	6.83	8.00	2.50	2.50	7.00
cycles	2.50	3.50	7.17	6.83	8.00	2.50	2.50	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.75
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (9.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (4.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404c40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %R9D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVSS -0x1c(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RAX,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x18(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x288(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R9D,%R11D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS -0x14(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x280(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R11,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x10(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
MOV 0x278(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R11,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0xc(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RDI,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x8(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA (%RDX,%R9,1),%R11D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS -0x4(%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VMOVSS (%R8,%R10,1),%XMM0	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (6.3%)
MOV 0x298(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R9D,%R11D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVSS %XMM0,(%RSI,%R11,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
ADD $0x20,%R10	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %ECX,%R9D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R10,0x290(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 404c40 <main+0x1b20>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code