OV - attention-icx-skl256 - Loop 37

0x404bb0 MOV	0x120(%RSP),%RCX

0x404bb8 LEA	0x1(%RCX),%RSI

0x404bbc MOV	0x90(%RSP),%RAX

0x404bc4 ADD	%R13D,%EAX

0x404bc7 CMP	0x190(%RSP),%RCX

0x404bcf JE	404d50

0x404bd5 MOV	%RAX,0x90(%RSP)

0x404bdd MOV	%EAX,%EAX

0x404bdf MOV	%RAX,0xe8(%RSP)

0x404be7 MOV	0xd0(%RSP),%RAX

0x404bef MOV	%RSI,0x120(%RSP)

0x404bf7 LEA	(%RAX,%RSI,4),%RSI

0x404bfb CMP	$0x8,%R14D

0x404bff MOV	0x150(%RSP),%RAX

0x404c07 MOV	0x1a8(%RSP),%ECX

0x404c0e MOV	0x260(%RSP),%RDI

0x404c16 MOV	0x258(%RSP),%RDX

0x404c1e JB	404cf9

0x404c24 MOV	0x140(%RSP),%R8

0x404c2c MOV	0xe8(%RSP),%R9

0x404c34 LEA	(%R8,%R9,4),%R8

0x404c38 XOR	%R9D,%R9D

0x404c3b XOR	%R10D,%R10D

0x404c3e XCHG	%AX,%AX

  (39) 0x404c40 MOV	%R9D,%R11D

  (39) 0x404c43 VMOVSS	-0x1c(%R8,%R10,1),%XMM0

  (39) 0x404c4a VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404c50 LEA	(%RAX,%R9,1),%R11D

  (39) 0x404c54 VMOVSS	-0x18(%R8,%R10,1),%XMM0

  (39) 0x404c5b VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404c61 MOV	0x288(%RSP),%R11

  (39) 0x404c69 ADD	%R9D,%R11D

  (39) 0x404c6c VMOVSS	-0x14(%R8,%R10,1),%XMM0

  (39) 0x404c73 VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404c79 MOV	0x280(%RSP),%R11

  (39) 0x404c81 LEA	(%R11,%R9,1),%R11D

  (39) 0x404c85 VMOVSS	-0x10(%R8,%R10,1),%XMM0

  (39) 0x404c8c VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404c92 MOV	0x278(%RSP),%R11

  (39) 0x404c9a LEA	(%R11,%R9,1),%R11D

  (39) 0x404c9e VMOVSS	-0xc(%R8,%R10,1),%XMM0

  (39) 0x404ca5 VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404cab LEA	(%RDI,%R9,1),%R11D

  (39) 0x404caf VMOVSS	-0x8(%R8,%R10,1),%XMM0

  (39) 0x404cb6 VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404cbc LEA	(%RDX,%R9,1),%R11D

  (39) 0x404cc0 VMOVSS	-0x4(%R8,%R10,1),%XMM0

  (39) 0x404cc7 VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404ccd VMOVSS	(%R8,%R10,1),%XMM0

  (39) 0x404cd3 MOV	0x298(%RSP),%R11

  (39) 0x404cdb ADD	%R9D,%R11D

  (39) 0x404cde VMOVSS	%XMM0,(%RSI,%R11,4)

  (39) 0x404ce4 ADD	$0x20,%R10

  (39) 0x404ce8 ADD	%ECX,%R9D

  (39) 0x404ceb CMP	%R10,0x290(%RSP)

  (39) 0x404cf3 JNE	404c40

0x404cf9 CMP	%R14,0x1d0(%RSP)

0x404d01 JAE	404bb0

0x404d07 MOV	0xc8(%RSP),%RCX

0x404d0f MOV	0xe8(%RSP),%RDX

0x404d17 LEA	(%RCX,%RDX,4),%RDI

0x404d1b MOV	0x248(%RSP),%R8

0x404d23 MOV	0x1d0(%RSP),%R9

0x404d2b NOPL	(%RAX,%RAX,1)

  (38) 0x404d30 VMOVSS	(%RDI,%R9,4),%XMM0

  (38) 0x404d36 MOV	%R8D,%R10D

  (38) 0x404d39 VMOVSS	%XMM0,(%RSI,%R10,4)

  (38) 0x404d3f INC	%R9

  (38) 0x404d42 ADD	%RAX,%R8

  (38) 0x404d45 CMP	%R9,%R14

  (38) 0x404d48 JNE	404d30

0x404d4a JMP	404bb0

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h: 1254 - 1254

--------------------------------------------------------------------------------

1254: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 233 - 238

--------------------------------------------------------------------------------

233:       start = std::chrono::steady_clock::now();

234: #endif

235:

236:       for (int i = 0; i < context_size; ++i)

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.50
Front-end cycles	6.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	3.00
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.50
Nb uops	26.00
Nb loads	12.00
Nb stores	3.00
Nb stack references	11.50
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	24.00
Stride 0	0.67
Stride 1	0.00
Stride n	0.00
Stride unknown	2.67
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.24
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.85

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	8.25
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	0.59
Front-end cycles	8.25
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	15.00
Nb stores	3.00
Nb stack references	13.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.97
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.71
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	0.48
Front-end cycles	6.25
P0 cycles	2.25
P1 cycles	2.25
P2 cycles	5.50
P3 cycles	5.50
P4 cycles	3.00
P5 cycles	2.25
P6 cycles	2.25
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	11.00
Nb stores	3.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.28
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	24.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	0.53
Front-end cycles	6.75
P0 cycles	2.75
P1 cycles	2.75
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	3.00
P5 cycles	2.75
P6 cycles	2.75
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	13.00
Nb stores	3.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.37
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	micro-operation queue,
Function	main
Source	stl_vector.h:1254-1254,attention_v2.cpp:233-233,attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	0.39
Front-end cycles	4.75
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	3.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	19.00
Nb loads	9.00
Nb stores	3.00
Nb stack references	10.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.37
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.61
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 0.50 cycles (13.05x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 92 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26.50
nb uops	26
loop length	167
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.50	2.50	6.00	6.00	3.00	2.50	2.50	3.00
cycles	2.50	2.50	6.00	6.00	3.00	2.50	2.50	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.50
Dispatch	6.00
Data deps.	0.00
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

11% of peak load performance is reached (14.16 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 0.59 cycles (13.89x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	33
nb uops	33
loop length	204
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	7.50	7.50	3.00	3.00	3.00	3.00
cycles	3.00	3.00	7.50	7.50	3.00	3.00	3.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.25
Dispatch	7.50
Data deps.	0.00
Overall L1	8.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

10% of peak load performance is reached (14.06 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 404bd5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x190(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 404d50 <main+0x1c30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0xe8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%RAX,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP $0x8,%R14D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x150(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1a8(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x260(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x258(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JB 404cf9 <main+0x1bd9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x140(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xe8(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R8,%R9,4),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R14,0x1d0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JAE 404bb0 <main+0x1a90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0xc8(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xe8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RCX,%RDX,4),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x248(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1d0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404bb0 <main+0x1a90>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.25 to 0.48 cycles (13.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 84 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26
nb uops	25
loop length	158
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.25	2.25	5.50	5.50	3.00	2.25	2.25	3.00
cycles	2.25	2.25	5.50	5.50	3.00	2.25	2.25	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.25
Dispatch	5.50
Data deps.	0.00
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

10% of peak load performance is reached (13.44 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.25 to 5.50 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 404bd5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x190(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 404d50 <main+0x1c30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0xe8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%RAX,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP $0x8,%R14D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x150(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1a8(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x260(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x258(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JB 404cf9 <main+0x1bd9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0x140(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xe8(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%R8,%R9,4),%R8	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R14,0x1d0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JAE 404bb0 <main+0x1a90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 0.53 cycles (12.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 100 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	27
nb uops	27
loop length	176
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.75 cycles
front end	6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.75	2.75	6.50	6.50	3.00	2.75	2.75	3.00
cycles	2.75	2.75	6.50	6.50	3.00	2.75	2.75	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.75
Dispatch	6.50
Data deps.	0.00
Overall L1	6.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

11% of peak load performance is reached (14.81 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.56 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 404bd5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x190(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 404d50 <main+0x1c30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0xe8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%RAX,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP $0x8,%R14D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x150(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1a8(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x260(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x258(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
JB 404cf9 <main+0x1bd9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP %R14,0x1d0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JAE 404bb0 <main+0x1a90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV 0xc8(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xe8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA (%RCX,%RDX,4),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x248(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x1d0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404bb0 <main+0x1a90>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:233-238
Module	attention-icx-skl256

The loop is defined in:

/usr/lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/stl_vector.h:1254
/home/eoseret/Applications/llm-attention/attention_v2.cpp:233-238

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 0.39 cycles (12.31x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	20
nb uops	19
loop length	130
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.00	2.00	4.50	4.50	3.00	2.00	2.00	3.00
cycles	2.00	2.00	4.50	4.50	3.00	2.00	2.00	3.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	4.50
Data deps.	0.00
Overall L1	4.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

11% of peak load performance is reached (14.32 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (5.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.75 to 4.50 cycles (1.06x speedup).

ASM code

In the binary file, the address of the loop is: 404bd5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV 0x120(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
LEA 0x1(%RCX),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
ADD %R13D,%EAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x190(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 404d50 <main+0x1c30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,0xe8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x120(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
LEA (%RAX,%RSI,4),%RSI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP $0x8,%R14D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV 0x150(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x1a8(%RSP),%ECX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x260(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0x258(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
JB 404cf9 <main+0x1bd9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP %R14,0x1d0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JAE 404bb0 <main+0x1a90>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary