OV - attention-icx-skl256 - Loop 35

	Loop Id: 35	Module: attention-icx-skl256	Source: attention_v2.cpp:27-33	Coverage: 2.26%

0x404e00 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x404e04 ADD	%EDX,%EDI

0x404e06 VMULSS	0x1ac(%RSP),%XMM0,%XMM0

0x404e0f MOV	0xc0(%RSP),%RCX

0x404e17 VMOVSS	%XMM0,(%RCX,%RDI,4)

0x404e1c LEA	0x1(%RSI),%RDI

0x404e20 CMP	0x190(%RSP),%RSI

0x404e28 MOV	%RDI,%RSI

0x404e2b JE	404dc0

0x404e2d TEST	%R15,%R15

0x404e30 JE	404ef0

0x404e36 MOV	%ESI,%EDI

0x404e38 VPBROADCASTD	%ESI,%XMM1

0x404e3e VXORPS	%XMM0,%XMM0,%XMM0

0x404e42 XOR	%R8D,%R8D

0x404e45 MOV	0xd8(%RSP),%R11

0x404e4d MOV	0xd0(%RSP),%RCX

0x404e55 NOPW	%CS:(%RAX,%RAX,1)

  (36) 0x404e60 LEA	(%RAX,%R8,1),%R9D

  (36) 0x404e64 VPBROADCASTD	%R9D,%XMM2

  (36) 0x404e6a LEA	(%R11,%R12,1),%R9

  (36) 0x404e6e VPCMPEQB	%XMM0,%XMM0,%K1

  (36) 0x404e74 VXORPD	%XMM3,%XMM3,%XMM3

  (36) 0x404e78 VPBROADCASTD	%R8D,%XMM4

  (36) 0x404e7e VPADDD	%XMM6,%XMM2,%XMM2

  (36) 0x404e82 VPADDD	%XMM7,%XMM4,%XMM4

  (36) 0x404e86 VPMULLD	%XMM4,%XMM5,%XMM4

  (36) 0x404e8b VPADDD	%XMM4,%XMM1,%XMM4

  (36) 0x404e8f LEA	(%RCX,%R12,1),%R10

  (36) 0x404e93 VPSUBD	%XMM8,%XMM4,%XMM4

  (36) 0x404e98 VPCMPEQB	%XMM0,%XMM0,%K2

  (36) 0x404e9e VGATHERDPS	(%R9,%XMM2,4),%XMM3{%K1}

  (36) 0x404ea5 VXORPS	%XMM2,%XMM2,%XMM2

  (36) 0x404ea9 VGATHERDPS	(%R10,%XMM4,4),%XMM2{%K2}

  (36) 0x404eb0 VCVTPS2PD	%XMM3,%YMM3

  (36) 0x404eb4 VCVTPS2PD	%XMM2,%YMM2

  (36) 0x404eb8 VFMADD231PD	%YMM2,%YMM3,%YMM0

  (36) 0x404ebd ADD	$0x4,%R8

  (36) 0x404ec1 CMP	%R15,%R8

  (36) 0x404ec4 JB	404e60

0x404ec6 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x404ecc VADDPD	%XMM1,%XMM0,%XMM0

0x404ed0 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x404ed5 VADDSD	%XMM1,%XMM0,%XMM0

0x404ed9 MOV	%R15,%R8

0x404edc TESTB	$0x1,0xe4(%RSP)

0x404ee4 JNE	404e00

0x404eea JMP	404ef7

0x404ef0 VXORPS	%XMM0,%XMM0,%XMM0

0x404ef4 XOR	%R8D,%R8D

0x404ef7 MOV	0x150(%RSP),%R10

0x404eff MOV	%R10,%RDI

0x404f02 IMUL	%R8,%RDI

0x404f06 ADD	%RSI,%RDI

0x404f09 MOV	0xd8(%RSP),%R11

0x404f11 MOV	0xd0(%RSP),%RCX

0x404f19 NOPL	(%RAX)

  (23) 0x404f20 LEA	(%RAX,%R8,1),%R9D

  (23) 0x404f24 VMOVSS	(%R11,%R9,4),%XMM1

  (23) 0x404f2a VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (23) 0x404f2e MOV	%EDI,%R9D

  (23) 0x404f31 VMOVSS	(%RCX,%R9,4),%XMM2

  (23) 0x404f37 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (23) 0x404f3b VFMADD231SD	%XMM2,%XMM1,%XMM0

  (23) 0x404f40 INC	%R8

  (23) 0x404f43 ADD	%R10,%RDI

  (23) 0x404f46 CMP	%R8,%R14

  (23) 0x404f49 JNE	404f20

0x404f4b MOV	%ESI,%EDI

0x404f4d JMP	404e00

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.85
CQA speedup if FP arith vectorized	2.11
CQA speedup if fully vectorized	11.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.77
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.08
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.35
CQA cycles if fully vectorized	0.61
Front-end cycles	7.08
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	1.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.33
Nb uops	28.33
Nb loads	7.00
Nb stores	1.00
Nb stack references	6.33
FLOP/cycle	0.42
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.29
Bytes prefetched	0.00
Bytes loaded	47.33
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.67
Stride indirect	2.00
Vectorization ratio all	21.07
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	27.78
Vector-efficiency ratio all	13.14
Vector-efficiency ratio load	10.33
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.31

Metric	Value
CQA speedup if no scalar integer	1.92
CQA speedup if FP arith vectorized	2.79
CQA speedup if fully vectorized	13.04
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.92
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	2.06
CQA cycles if fully vectorized	0.44
Front-end cycles	5.75
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	23.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.17
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.35
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	11.81
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.75

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.69
Front-end cycles	9.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	4.50
P3 cycles	4.50
P4 cycles	1.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	36.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	7.00
FLOP/cycle	0.44
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.22
Bytes prefetched	0.00
Bytes loaded	61.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	3.00
Vectorization ratio all	23.53
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	30.00
Vector-efficiency ratio all	13.33
Vector-efficiency ratio load	9.64
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.91

Metric	Value
CQA speedup if no scalar integer	1.63
CQA speedup if FP arith vectorized	1.63
CQA speedup if fully vectorized	9.45
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.69
Front-end cycles	6.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	26.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	6.00
FLOP/cycle	0.62
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.31
Bytes prefetched	0.00
Bytes loaded	37.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	28.57
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	14.29
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.28

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30-33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: multiply

The binary loop is loading 47 bytes (11 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	27.33
nb uops	28.33
loop length	141
used x86 registers	9.67
used mmx registers	0
used xmm registers	1.67
used ymm registers	0.67
used zmm registers	0
nb stack references	6.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.08 cycles
front end	7.08 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	3.50	3.50	1.00	4.00	4.00	1.00
cycles	4.00	4.00	3.50	3.50	1.00	4.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.08
Dispatch	4.00
Data deps.	0.00
Overall L1	7.08

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	41%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	21%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Vector efficiency ratios

INT

all	10%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	15%
load	6%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	13%
load	10%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.08 cycles. At this rate:

5% of peak load performance is reached (6.71 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.59 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-icx-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 3.00 cycles (1.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.44 cycles (13.04x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	23
loop length	109
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	3.00	3.00	1.00	3.00	3.00	1.00
cycles	3.00	3.00	3.00	3.00	1.00	3.00	3.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.75
Dispatch	3.00
Data deps.	0.00
Overall L1	5.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	11%
load	10%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

5% of peak load performance is reached (7.65 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.70 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.75 to 3.00 cycles (1.92x speedup).

ASM code

In the binary file, the address of the loop is: 404e2d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMULSS 0x1ac(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
MOV 0xc0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x190(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404dc0 <main+0x1ca0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 404ef0 <main+0x1dd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x150(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd8(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404e00 <main+0x1ce0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-icx-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 4.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
30% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

3: addition or subtraction
1: multiply

The binary loop is loading 61 bytes (15 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	35
nb uops	36
loop length	182
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	5.00	4.50	4.50	1.00	5.00	5.00	1.00
cycles	5.00	5.00	4.50	4.50	1.00	5.00	5.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.00
Dispatch	5.00
Data deps.	0.00
Overall L1	9.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	23%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Vector efficiency ratios

INT

all	9%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	17%
load	6%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	13%
load	9%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

5% of peak load performance is reached (6.78 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.44 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404e2d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMULSS 0x1ac(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
MOV 0xc0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x190(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404dc0 <main+0x1ca0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 404ef0 <main+0x1dd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTD %ESI,%XMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xd8(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0x1,0xe4(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (1.6%)
JNE 404e00 <main+0x1ce0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 404ef7 <main+0x1dd7>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x150(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %R8,%RDI	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd8(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 404e00 <main+0x1ce0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-icx-skl256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 4.00 cycles (1.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

3: addition or subtraction
1: multiply

The binary loop is loading 37 bytes (9 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	26
loop length	132
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	0
nb stack references	6
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	3.00	3.00	1.00	4.00	4.00	1.00
cycles	4.00	4.00	3.00	3.00	1.00	4.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.50
Dispatch	4.00
Data deps.	0.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

INT+FP

all	28%
load	0%
store	0%
mul	0%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	17%
load	6%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

INT+FP

all	14%
load	10%
store	6%
mul	6%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

4% of peak load performance is reached (5.69 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404e2d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMULSS 0x1ac(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
MOV 0xc0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
CMP 0x190(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JE 404dc0 <main+0x1ca0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %R15,%R15	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JE 404ef0 <main+0x1dd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VPBROADCASTD %ESI,%XMM1	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xd8(%RSP),%R11	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	1	0	0	1	1	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
TESTB $0x1,0xe4(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 404e00 <main+0x1ce0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

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Vectorization

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512-bits vectorization

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FMA

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Complex instructions

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Slow data structures access

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Conversion instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary