OV - attention-icx-skl256 - Loop 29

0x4055f0 VPBROADCASTD	%R9D,%YMM3

0x4055f6 VPADDD	%YMM3,%YMM8,%YMM3

0x4055fa VPMULLD	%YMM3,%YMM7,%YMM3

0x4055ff VPADDD	%YMM3,%YMM1,%YMM3

0x405603 VPCMPEQB	%XMM0,%XMM0,%K1

0x405609 VPSUBD	%YMM9,%YMM3,%YMM3

0x40560e VXORPS	%XMM4,%XMM4,%XMM4

0x405612 VGATHERDPS	(%RCX,%YMM3,4),%YMM4{%K1}    [1]

0x405619 LEA	(%RAX,%R9,1),%R10D

0x40561d VCVTPS2PD	(%RDX,%R10,4),%YMM3    [2]

0x405623 VCVTPS2PD	0x10(%RDX,%R10,4),%YMM5    [2]

0x40562a VEXTRACTF128	$0x1,%YMM4,%XMM6

0x405630 VCVTPS2PD	%XMM4,%YMM4

0x405634 VCVTPS2PD	%XMM6,%YMM6

0x405638 VFMADD231PD	%YMM6,%YMM5,%YMM2

0x40563d VFMADD231PD	%YMM4,%YMM3,%YMM0

0x405642 ADD	$0x8,%R9

0x405646 CMP	%R11,%R9

0x405649 JB	4055f0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	5.83
CQA cycles if FP arith vectorized	5.58
CQA cycles if fully vectorized	2.25
Front-end cycles	5.75
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	23.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	93.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	88.89
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.69

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	6.00
CQA cycles if no scalar integer	5.83
CQA cycles if FP arith vectorized	5.58
CQA cycles if fully vectorized	2.25
Front-end cycles	5.75
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	0.00
P5 cycles	6.00
P6 cycles	2.00
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	23.00
Nb loads	3.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.67
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	93.33
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	88.89
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.69

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 35% of vector register length is used (average across all SSE/AVX instructions).

Details

93% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VGATHERDPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	19
nb uops	23
loop length	91
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	6.00	5.00	5.00	0.00	6.00	2.00	0.00
cycles	6.00	6.00	5.00	5.00	0.00	6.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.75
Dispatch	6.00
Data deps.	4.00
Overall L1	6.00

Vectorization ratios

INT

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

Vector efficiency ratios

INT

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

FP

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	35%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

8% of peak load performance is reached (10.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4055f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VPBROADCASTD %R9D,%YMM3	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM8,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM3,%YMM7,%YMM3	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VPSUBD %YMM9,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VGATHERDPS (%RCX,%YMM3,4),%YMM4{%K1}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
LEA (%RAX,%R9,1),%R10D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VCVTPS2PD (%RDX,%R10,4),%YMM3	1	0.50	0.50	0.50	0.50	0	0	0	0	7	0.50	vect (25.0%)
VCVTPS2PD 0x10(%RDX,%R10,4),%YMM5	1	0.50	0.50	0.50	0.50	0	0	0	0	7	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM4,%XMM6	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM4	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM6,%YMM6	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VFMADD231PD %YMM6,%YMM5,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R11,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JB 4055f0 <main+0x24d0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:30-31.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 35% of vector register length is used (average across all SSE/AVX instructions).

Details

93% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

88% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VGATHERDPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	19
nb uops	23
loop length	91
used x86 registers	6
used mmx registers	0
used xmm registers	3
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	6.00	6.00	5.00	5.00	0.00	6.00	2.00	0.00
cycles	6.00	6.00	5.00	5.00	0.00	6.00	2.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.75
Dispatch	6.00
Data deps.	4.00
Overall L1	6.00

Vectorization ratios

INT

all	83%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	93%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	88%

Vector efficiency ratios

INT

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

FP

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

INT+FP

all	35%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

8% of peak load performance is reached (10.67 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4055f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VPBROADCASTD %R9D,%YMM3	1	0	0	0	0	0	1	0	0	1	1	scal (6.3%)
VPADDD %YMM3,%YMM8,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM3,%YMM7,%YMM3	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM3,%YMM1,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VPCMPEQB %XMM0,%XMM0,%K1												vect (25.0%)
VPSUBD %YMM9,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	1	0.33	vect (50.0%)
VXORPS %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VGATHERDPS (%RCX,%YMM3,4),%YMM4{%K1}	4	1	0	4	4	0	1	0	0	21	5	vect (50.0%)
LEA (%RAX,%R9,1),%R10D	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VCVTPS2PD (%RDX,%R10,4),%YMM3	1	0.50	0.50	0.50	0.50	0	0	0	0	7	0.50	vect (25.0%)
VCVTPS2PD 0x10(%RDX,%R10,4),%YMM5	1	0.50	0.50	0.50	0.50	0	0	0	0	7	0.50	vect (25.0%)
VEXTRACTF128 $0x1,%YMM4,%XMM6	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM4	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM6,%YMM6	2	0.50	0.50	0	0	0	1	0	0	7	1	vect (25.0%)
VFMADD231PD %YMM6,%YMM5,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM4,%YMM3,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
ADD $0x8,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP %R11,%R9	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JB 4055f0 <main+0x24d0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code