OV - attention-icx-skl256 - Loop 24

0x405200 VMOVUPS	(%RSI,%RDI,4),%YMM0    [3]

0x405205 VSUBPS	%YMM10,%YMM0,%YMM0

0x40520a CALL	4068b0 <__svml_expf8_l9>

0x405210 VMULPS	%YMM0,%YMM11,%YMM0

0x405214 MOV	0x90(%RSP),%RAX    [1]

0x40521c VMOVUPS	%YMM0,(%RAX,%RDI,4)    [2]

0x405221 ADD	$0x8,%RDI

0x405225 CMP	0x120(%RSP),%RDI    [1]

0x40522d JLE	405200

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	1.13
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	1.83
P3 cycles	1.50
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	7.11
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.56
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	1.13
Front-end cycles	2.25
P0 cycles	1.50
P1 cycles	1.00
P2 cycles	1.83
P3 cycles	1.50
P4 cycles	2.00
P5 cycles	1.00
P6 cycles	1.50
P7 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	7.11
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	35.56
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:55-56.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.25 to 1.50 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.13x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf8_l9: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:56

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: multiply

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	9
nb uops	9
loop length	47
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	1.83	1.50	2.00	1.00	1.50	1.67
cycles	1.50	1.00	1.83	1.50	2.00	1.00	1.50	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	2.00
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

16% of peak load performance is reached (21.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (14.22 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 2.00 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 405200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RDI,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
CALL 4068b0 <__svml_expf8_l9>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMULPS %YMM0,%YMM11,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVUPS %YMM0,(%RAX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
ADD $0x8,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x120(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JLE 405200 <main+0x20e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-icx-skl256

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:55-56.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.25 to 1.50 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.13x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf8_l9: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:56

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction
8: multiply

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 32 bytes (8 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	9
nb uops	9
loop length	47
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	3
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	1.50	1.00	1.83	1.50	2.00	1.00	1.50	1.67
cycles	1.50	1.00	1.83	1.50	2.00	1.00	1.50	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Dispatch	2.00
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

16% of peak load performance is reached (21.33 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (14.22 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 2.00 cycles (1.13x speedup).

ASM code

In the binary file, the address of the loop is: 405200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVUPS (%RSI,%RDI,4),%YMM0	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
CALL 4068b0 <__svml_expf8_l9>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
VMULPS %YMM0,%YMM11,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV 0x90(%RSP),%RAX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVUPS %YMM0,(%RAX,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
ADD $0x8,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x120(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JLE 405200 <main+0x20e0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code