OV - attention-icx-skl256 - Function __ocl_svml_l9__svml_sexp_cout_rare_internal

	Function: __ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper	Module: attention-icx-skl256	Source: :0-0	Coverage (incl. loops): 0.53% \| (excl. loops): 0.53%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4069c0 SUB	$0x138,%RSP

0x4069c7 VMOVUPS	%YMM15,0x100(%RSP)

0x4069d0 VMOVUPS	%YMM14,0xe0(%RSP)

0x4069d9 VMOVUPS	%YMM13,0xc0(%RSP)

0x4069e2 VMOVUPS	%YMM12,0xa0(%RSP)

0x4069eb VMOVUPS	%YMM11,0x80(%RSP)

0x4069f4 VMOVUPS	%YMM10,0x60(%RSP)

0x4069fa VMOVUPS	%YMM9,0x40(%RSP)

0x406a00 VMOVUPS	%YMM8,0x20(%RSP)

0x406a06 TEST	$0x1,%DL

0x406a09 JNE	406a94

0x406a0f TEST	$0x2,%DL

0x406a12 JNE	406acb

0x406a18 TEST	$0x4,%DL

0x406a1b JNE	406b06

0x406a21 TEST	$0x8,%DL

0x406a24 JNE	406b41

0x406a2a TEST	$0x10,%DL

0x406a2d JNE	406b7c

0x406a33 TEST	$0x20,%DL

0x406a36 JNE	406bb7

0x406a3c TEST	$0x40,%DL

0x406a3f JNE	406bf2

0x406a45 TEST	%DL,%DL

0x406a47 JS	406c2c

0x406a4d VMOVUPS	0x20(%RSP),%YMM8

0x406a53 VMOVUPS	0x40(%RSP),%YMM9

0x406a59 VMOVUPS	0x60(%RSP),%YMM10

0x406a5f VMOVUPS	0x80(%RSP),%YMM11

0x406a68 VMOVUPS	0xa0(%RSP),%YMM12

0x406a71 VMOVUPS	0xc0(%RSP),%YMM13

0x406a7a VMOVUPS	0xe0(%RSP),%YMM14

0x406a83 VMOVUPS	0x100(%RSP),%YMM15

0x406a8c ADD	$0x138,%RSP

0x406a93 RET

0x406a94 MOV	%RDI,0x18(%RSP)

0x406a99 MOV	0x18(%RSP),%RDI

0x406a9e MOV	%RSI,0x10(%RSP)

0x406aa3 MOV	0x10(%RSP),%RSI

0x406aa8 MOV	%EDX,0xc(%RSP)

0x406aac VZEROUPPER

0x406aaf CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406ab4 MOV	0xc(%RSP),%EDX

0x406ab8 MOV	0x18(%RSP),%RDI

0x406abd MOV	0x10(%RSP),%RSI

0x406ac2 TEST	$0x2,%DL

0x406ac5 JE	406a18

0x406acb LEA	0x4(%RDI),%RAX

0x406acf LEA	0x4(%RSI),%RCX

0x406ad3 MOV	%RDI,0x18(%RSP)

0x406ad8 MOV	%RAX,%RDI

0x406adb MOV	%RSI,0x10(%RSP)

0x406ae0 MOV	%RCX,%RSI

0x406ae3 MOV	%EDX,0xc(%RSP)

0x406ae7 VZEROUPPER

0x406aea CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406aef MOV	0xc(%RSP),%EDX

0x406af3 MOV	0x18(%RSP),%RDI

0x406af8 MOV	0x10(%RSP),%RSI

0x406afd TEST	$0x4,%DL

0x406b00 JE	406a21

0x406b06 LEA	0x8(%RDI),%RAX

0x406b0a LEA	0x8(%RSI),%RCX

0x406b0e MOV	%RDI,0x18(%RSP)

0x406b13 MOV	%RAX,%RDI

0x406b16 MOV	%RSI,0x10(%RSP)

0x406b1b MOV	%RCX,%RSI

0x406b1e MOV	%EDX,0xc(%RSP)

0x406b22 VZEROUPPER

0x406b25 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406b2a MOV	0xc(%RSP),%EDX

0x406b2e MOV	0x18(%RSP),%RDI

0x406b33 MOV	0x10(%RSP),%RSI

0x406b38 TEST	$0x8,%DL

0x406b3b JE	406a2a

0x406b41 LEA	0xc(%RDI),%RAX

0x406b45 LEA	0xc(%RSI),%RCX

0x406b49 MOV	%RDI,0x18(%RSP)

0x406b4e MOV	%RAX,%RDI

0x406b51 MOV	%RSI,0x10(%RSP)

0x406b56 MOV	%RCX,%RSI

0x406b59 MOV	%EDX,0xc(%RSP)

0x406b5d VZEROUPPER

0x406b60 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406b65 MOV	0xc(%RSP),%EDX

0x406b69 MOV	0x18(%RSP),%RDI

0x406b6e MOV	0x10(%RSP),%RSI

0x406b73 TEST	$0x10,%DL

0x406b76 JE	406a33

0x406b7c LEA	0x10(%RDI),%RAX

0x406b80 LEA	0x10(%RSI),%RCX

0x406b84 MOV	%RDI,0x18(%RSP)

0x406b89 MOV	%RAX,%RDI

0x406b8c MOV	%RSI,0x10(%RSP)

0x406b91 MOV	%RCX,%RSI

0x406b94 MOV	%EDX,0xc(%RSP)

0x406b98 VZEROUPPER

0x406b9b CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406ba0 MOV	0xc(%RSP),%EDX

0x406ba4 MOV	0x18(%RSP),%RDI

0x406ba9 MOV	0x10(%RSP),%RSI

0x406bae TEST	$0x20,%DL

0x406bb1 JE	406a3c

0x406bb7 LEA	0x14(%RDI),%RAX

0x406bbb LEA	0x14(%RSI),%RCX

0x406bbf MOV	%RDI,0x18(%RSP)

0x406bc4 MOV	%RAX,%RDI

0x406bc7 MOV	%RSI,0x10(%RSP)

0x406bcc MOV	%RCX,%RSI

0x406bcf MOV	%EDX,0xc(%RSP)

0x406bd3 VZEROUPPER

0x406bd6 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406bdb MOV	0xc(%RSP),%EDX

0x406bdf MOV	0x18(%RSP),%RDI

0x406be4 MOV	0x10(%RSP),%RSI

0x406be9 TEST	$0x40,%DL

0x406bec JE	406a45

0x406bf2 LEA	0x18(%RDI),%RAX

0x406bf6 LEA	0x18(%RSI),%RCX

0x406bfa MOV	%RDI,0x18(%RSP)

0x406bff MOV	%RAX,%RDI

0x406c02 MOV	%RSI,0x10(%RSP)

0x406c07 MOV	%RCX,%RSI

0x406c0a MOV	%EDX,0xc(%RSP)

0x406c0e VZEROUPPER

0x406c11 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406c16 MOV	0xc(%RSP),%EDX

0x406c1a MOV	0x18(%RSP),%RDI

0x406c1f MOV	0x10(%RSP),%RSI

0x406c24 TEST	%DL,%DL

0x406c26 JNS	406a4d

0x406c2c ADD	$0x1c,%RDI

0x406c30 ADD	$0x1c,%RSI

0x406c34 VZEROUPPER

0x406c37 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x406c3c JMP	406a4d

0x406c41 NOPW	%CS:(%RAX,%RAX,1)

0x406c4b NOPL	(%RAX,%RAX,1)

0x407600 SUB	$0x138,%RSP

0x407607 VMOVUPS	%YMM15,0x100(%RSP)

0x407610 VMOVUPS	%YMM14,0xe0(%RSP)

0x407619 VMOVUPS	%YMM13,0xc0(%RSP)

0x407622 VMOVUPS	%YMM12,0xa0(%RSP)

0x40762b VMOVUPS	%YMM11,0x80(%RSP)

0x407634 VMOVUPS	%YMM10,0x60(%RSP)

0x40763a VMOVUPS	%YMM9,0x40(%RSP)

0x407640 VMOVUPS	%YMM8,0x20(%RSP)

0x407646 TEST	%EDX,%EDX

0x407648 JNE	407691

0x40764a VMOVUPS	0x20(%RSP),%YMM8

0x407650 VMOVUPS	0x40(%RSP),%YMM9

0x407656 VMOVUPS	0x60(%RSP),%YMM10

0x40765c VMOVUPS	0x80(%RSP),%YMM11

0x407665 VMOVUPS	0xa0(%RSP),%YMM12

0x40766e VMOVUPS	0xc0(%RSP),%YMM13

0x407677 VMOVUPS	0xe0(%RSP),%YMM14

0x407680 VMOVUPS	0x100(%RSP),%YMM15

0x407689 ADD	$0x138,%RSP

0x407690 RET

0x407691 TEST	$0x1,%DL

0x407694 JNE	4076e5

0x407696 TEST	$0x2,%DL

0x407699 JNE	407718

0x40769b TEST	$0x4,%DL

0x40769e JNE	407753

0x4076a4 TEST	$0x8,%DL

0x4076a7 JNE	40778e

0x4076ad TEST	$0x10,%DL

0x4076b0 JNE	4077c9

0x4076b6 TEST	$0x20,%DL

0x4076b9 JNE	407804

0x4076bf TEST	$0x40,%DL

0x4076c2 JNE	40783f

0x4076c8 TEST	%DL,%DL

0x4076ca JNS	40764a

0x4076d0 ADD	$0x1c,%RDI

0x4076d4 ADD	$0x1c,%RSI

0x4076d8 VZEROUPPER

0x4076db CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x4076e0 JMP	40764a

0x4076e5 MOV	%RDI,0x18(%RSP)

0x4076ea MOV	0x18(%RSP),%RDI

0x4076ef MOV	%RSI,0x10(%RSP)

0x4076f4 MOV	0x10(%RSP),%RSI

0x4076f9 MOV	%EDX,0xc(%RSP)

0x4076fd VZEROUPPER

0x407700 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x407705 MOV	0xc(%RSP),%EDX

0x407709 MOV	0x18(%RSP),%RDI

0x40770e MOV	0x10(%RSP),%RSI

0x407713 TEST	$0x2,%DL

0x407716 JE	40769b

0x407718 LEA	0x4(%RDI),%RAX

0x40771c LEA	0x4(%RSI),%RCX

0x407720 MOV	%RDI,0x18(%RSP)

0x407725 MOV	%RAX,%RDI

0x407728 MOV	%RSI,0x10(%RSP)

0x40772d MOV	%RCX,%RSI

0x407730 MOV	%EDX,0xc(%RSP)

0x407734 VZEROUPPER

0x407737 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x40773c MOV	0xc(%RSP),%EDX

0x407740 MOV	0x18(%RSP),%RDI

0x407745 MOV	0x10(%RSP),%RSI

0x40774a TEST	$0x4,%DL

0x40774d JE	4076a4

0x407753 LEA	0x8(%RDI),%RAX

0x407757 LEA	0x8(%RSI),%RCX

0x40775b MOV	%RDI,0x18(%RSP)

0x407760 MOV	%RAX,%RDI

0x407763 MOV	%RSI,0x10(%RSP)

0x407768 MOV	%RCX,%RSI

0x40776b MOV	%EDX,0xc(%RSP)

0x40776f VZEROUPPER

0x407772 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x407777 MOV	0xc(%RSP),%EDX

0x40777b MOV	0x18(%RSP),%RDI

0x407780 MOV	0x10(%RSP),%RSI

0x407785 TEST	$0x8,%DL

0x407788 JE	4076ad

0x40778e LEA	0xc(%RDI),%RAX

0x407792 LEA	0xc(%RSI),%RCX

0x407796 MOV	%RDI,0x18(%RSP)

0x40779b MOV	%RAX,%RDI

0x40779e MOV	%RSI,0x10(%RSP)

0x4077a3 MOV	%RCX,%RSI

0x4077a6 MOV	%EDX,0xc(%RSP)

0x4077aa VZEROUPPER

0x4077ad CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x4077b2 MOV	0xc(%RSP),%EDX

0x4077b6 MOV	0x18(%RSP),%RDI

0x4077bb MOV	0x10(%RSP),%RSI

0x4077c0 TEST	$0x10,%DL

0x4077c3 JE	4076b6

0x4077c9 LEA	0x10(%RDI),%RAX

0x4077cd LEA	0x10(%RSI),%RCX

0x4077d1 MOV	%RDI,0x18(%RSP)

0x4077d6 MOV	%RAX,%RDI

0x4077d9 MOV	%RSI,0x10(%RSP)

0x4077de MOV	%RCX,%RSI

0x4077e1 MOV	%EDX,0xc(%RSP)

0x4077e5 VZEROUPPER

0x4077e8 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x4077ed MOV	0xc(%RSP),%EDX

0x4077f1 MOV	0x18(%RSP),%RDI

0x4077f6 MOV	0x10(%RSP),%RSI

0x4077fb TEST	$0x20,%DL

0x4077fe JE	4076bf

0x407804 LEA	0x14(%RDI),%RAX

0x407808 LEA	0x14(%RSI),%RCX

0x40780c MOV	%RDI,0x18(%RSP)

0x407811 MOV	%RAX,%RDI

0x407814 MOV	%RSI,0x10(%RSP)

0x407819 MOV	%RCX,%RSI

0x40781c MOV	%EDX,0xc(%RSP)

0x407820 VZEROUPPER

0x407823 CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x407828 MOV	0xc(%RSP),%EDX

0x40782c MOV	0x18(%RSP),%RDI

0x407831 MOV	0x10(%RSP),%RSI

0x407836 TEST	$0x40,%DL

0x407839 JE	4076c8

0x40783f LEA	0x18(%RDI),%RAX

0x407843 LEA	0x18(%RSI),%RCX

0x407847 MOV	%RDI,0x18(%RSP)

0x40784c MOV	%RAX,%RDI

0x40784f MOV	%RSI,0x10(%RSP)

0x407854 MOV	%RCX,%RSI

0x407857 MOV	%EDX,0xc(%RSP)

0x40785b VZEROUPPER

0x40785e CALL	406ee0 <__svml_sexp_cout_rare_internal>

0x407863 MOV	0xc(%RSP),%EDX

0x407867 MOV	0x18(%RSP),%RDI

0x40786c MOV	0x10(%RSP),%RSI

0x407871 TEST	%DL,%DL

0x407873 JNS	40764a

0x407879 JMP	4076d0

0x40787e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►50.00+	main	attention_v2.cpp:56	attention-icx-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		attention-icx-skl256
►40.91+	main	attention_v2.cpp:53	attention-icx-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		attention-icx-skl256
►9.09+	__svml_expf8		attention-icx-skl256
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		attention-icx-skl256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.53% of application time for run run_0

Source file and lines
Module	attention-icx-skl256

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 85.50 to 31.75 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX stores are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_sexp_cout_rare_internal: 16 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 16 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 824 bytes. The binary function is storing 792 bytes.

General properties

nb instructions	278
nb uops	342
loop length	1296
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	85.50 cycles
front end	85.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	28.75	28.75	46.00	46.00	74.00	28.75	28.75	46.00
cycles	28.75	28.75	46.00	46.00	74.00	28.75	28.75	46.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	85.50
Dispatch	74.00
Overall L1	85.50

Vectorization ratios

INT

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	52%
load	100%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	50%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 85.50 cycles. At this rate:

7% of peak load performance is reached (9.64 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (9.26 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 85.50 to 74.00 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 4069c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
SUB $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
TEST $0x1,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406a94 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406acb <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x10b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b06 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x146>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b41 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x181>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b7c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1bc>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406bb7 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1f7>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406bf2 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x232>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JS 406c2c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x26c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
ADD $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a18 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x4(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x4(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a21 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x61>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x8(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a2a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x6a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0xc(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0xc(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a33 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x73>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x10(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x10(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a3c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x14(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x14(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a45 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x18(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x18(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 406a4d <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x8d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
ADD $0x1c,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
JMP 406a4d <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x8d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
TEST %EDX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JNE 407691 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
ADD $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
TEST $0x1,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4076e5 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407718 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407753 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x153>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 40778e <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x18e>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4077c9 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407804 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 40783f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
ADD $0x1c,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
JMP 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 40769b <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x9b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x4(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x4(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076a4 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xa4>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x8(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076ad <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xad>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0xc(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0xc(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076b6 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x10(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x10(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076bf <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x14(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x14(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076c8 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xc8>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x18(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x18(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 4076d0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.53% of application time for run run_0

Source file and lines
Module	attention-icx-skl256

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX stores are used in vector version.
94% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

CALL instructions

Detected function call instructions.

Details

__svml_sexp_cout_rare_internal: 16 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 16 occurrences►

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 824 bytes. The binary function is storing 792 bytes.

General properties

nb instructions	278
nb uops	342
loop length	1296
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	85.50 cycles
front end	85.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	28.75	28.75	46.00	46.00	74.00	28.75	28.75	46.00
cycles	28.75	28.75	46.00	46.00	74.00	28.75	28.75	46.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	85.50
Dispatch	74.00
Overall L1	85.50

Vectorization ratios

INT

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	52%
load	100%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	94%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	50%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 85.50 cycles. At this rate:

7% of peak load performance is reached (9.64 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (9.26 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4069c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
SUB $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
TEST $0x1,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406a94 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd4>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406acb <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x10b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b06 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x146>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b41 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x181>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406b7c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1bc>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406bb7 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1f7>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 406bf2 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x232>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JS 406c2c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x26c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
ADD $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a18 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x4(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x4(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a21 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x61>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x8(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a2a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x6a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0xc(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0xc(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a33 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x73>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x10(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x10(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a3c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x14(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x14(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 406a45 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x18(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x18(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 406a4d <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x8d>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
ADD $0x1c,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
JMP 406a4d <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x8d>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SUB $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	vect (50.0%)
TEST %EDX,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
JNE 407691 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.50	0.50	0	0	0	0	5-6	0.50	vect (50.0%)
ADD $0x138,%RSP	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
RET	1	0	0	0.33	0.33	0	0	1	0.33	0	1	N/A
TEST $0x1,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4076e5 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407718 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407753 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x153>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 40778e <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x18e>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 4077c9 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c9>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 407804 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 40783f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
ADD $0x1c,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD $0x1c,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
JMP 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x2,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 40769b <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x9b>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x4(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x4(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x4,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076a4 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xa4>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x8(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x8(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x8,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076ad <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xad>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0xc(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0xc(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x10,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076b6 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x10(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x10(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x20,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076bf <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x14(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x14(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST $0x40,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4076c8 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xc8>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
LEA 0x18(%RDI),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA 0x18(%RSI),%RCX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
VZEROUPPER	4	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ee0 <__svml_sexp_cout_rare_internal>	2	0	0	0.33	0.33	1	0	1	0.33	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
TEST %DL,%DL	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNS 40764a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
JMP 4076d0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A

Name	Coverage (%)	Time (s)
○__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper	0.53	0.11

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code