| Function: __svml_expf8_l9 | Module: attention-icx-skl256 | Source: :0-0 | Coverage (incl. loops): 1.31% | (excl. loops): 1.31% |
|---|
| Function: __svml_expf8_l9 | Module: attention-icx-skl256 | Source: :0-0 | Coverage (incl. loops): 1.31% | (excl. loops): 1.31% |
|---|
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4068b0 ENDBR64 |
0x4068b4 VMOVUPS 0xbdc4(%RIP),%YMM1 |
0x4068bc VMOVUPS 0xbffc(%RIP),%YMM2 |
0x4068c4 VMOVUPS 0xbd74(%RIP),%YMM3 |
0x4068cc VFMADD213PS %YMM1,%YMM0,%YMM3 |
0x4068d1 VSUBPS %YMM1,%YMM3,%YMM1 |
0x4068d5 VANDPS 0xc023(%RIP),%YMM0,%YMM4 |
0x4068dd VPCMPGTD 0xc05b(%RIP),%YMM4,%YMM4 |
0x4068e5 VMOVMSKPS %YMM4,%EAX |
0x4068e9 VPSLLD $0x17,%YMM3,%YMM3 |
0x4068ee VMOVUPS 0xbdca(%RIP),%YMM4 |
0x4068f6 VFNMADD213PS %YMM0,%YMM1,%YMM4 |
0x4068fb VFNMADD231PS 0xbdfc(%RIP),%YMM1,%YMM4 |
0x406904 VFMADD213PS 0xbf73(%RIP),%YMM4,%YMM2 |
0x40690d VFMADD213PS 0xbf2a(%RIP),%YMM4,%YMM2 |
0x406916 VFMADD213PS 0xbee1(%RIP),%YMM4,%YMM2 |
0x40691f VFMADD213PS 0xbe98(%RIP),%YMM4,%YMM2 |
0x406928 VFMADD213PS 0xbe4f(%RIP),%YMM4,%YMM2 |
0x406931 VPADDD %YMM2,%YMM3,%YMM1 |
0x406935 TEST %EAX,%EAX |
0x406937 JNE 40693e |
0x406939 VMOVAPS %YMM1,%YMM0 |
0x40693d RET |
0x40693e MOVZX %AL,%EAX |
0x406941 VMOVUPS 0xc037(%RIP),%YMM2 |
0x406949 VBROADCASTSS 0x76ce(%RIP),%YMM3 |
0x406952 VCMPPS $0x1,%YMM0,%YMM2,%YMM2 |
0x406957 VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1 |
0x40695d VCMPPS $0x1,0xc05a(%RIP),%YMM0,%YMM3 |
0x406966 VANDNPS %YMM1,%YMM3,%YMM1 |
0x40696a VORPS %YMM2,%YMM3,%YMM2 |
0x40696e VMOVMSKPS %YMM2,%ECX |
0x406972 ANDN %EAX,%ECX,%EDX |
0x406977 JE 406939 |
0x406979 PUSH %RBP |
0x40697a MOV %RSP,%RBP |
0x40697d PUSH %RSI |
0x40697e PUSH %RDI |
0x40697f AND $-0x40,%RSP |
0x406983 SUB $0x80,%RSP |
0x40698a VMOVUPS %YMM0,0x40(%RSP) |
0x406990 VMOVUPS %YMM1,(%RSP) |
0x406995 LEA 0x40(%RSP),%RDI |
0x40699a MOV %RSP,%RSI |
0x40699d CALL 4069c0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper> |
0x4069a3 VMOVUPS (%RSP),%YMM1 |
0x4069a8 LEA -0x10(%RBP),%RSP |
0x4069ac POP %RDI |
0x4069ad POP %RSI |
0x4069ae POP %RBP |
0x4069af VMOVAPS %YMM1,%YMM0 |
0x4069b3 RET |
0x4069b4 NOPW %CS:(%RAX,%RAX,1) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►75.93+ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl256 | |
| ►11.11+ | main | attention_v2.cpp:56 | attention-icx-skl256 |
| ○ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl256 | |
| ►11.11+ | main | attention_v2.cpp:53 | attention-icx-skl256 |
| ○ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl256 | |
| ►1.85+ | __svml_expf8 | attention-icx-skl256 | |
| ○ | __libc_init_first | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | attention-icx-skl256 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
The code analyzed by CQA in that panel excludes loops and represents 1.31% of application time for run run_0
| Source file and lines | |
| Module | attention-icx-skl256 |
| nb instructions | 35.67 |
| nb uops | 36 |
| loop length | 199.33 |
| used x86 registers | 3.67 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 9.00 cycles |
| front end | 9.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 7.22 | 7.11 | 7.67 | 7.67 | 2.00 | 5.50 | 4.50 | 3.00 |
| cycles | 7.22 | 7.11 | 7.67 | 7.67 | 2.00 | 5.50 | 4.50 | 3.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 9.00 |
| Dispatch | 7.67 |
| Overall L1 | 9.17 |
| all | 75% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 68% |
| all | 97% |
| load | 95% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 93% |
| all | 93% |
| load | 95% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 85% |
| all | 39% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 36% |
| all | 48% |
| load | 47% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 47% |
| all | 47% |
| load | 48% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 44% |
The code analyzed by CQA in that panel excludes loops and represents 1.31% of application time for run run_0
| Source file and lines | |
| Module | attention-icx-skl256 |
| nb instructions | 23 |
| nb uops | 22 |
| loop length | 142 |
| used x86 registers | 1 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.50 cycles |
| front end | 5.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 2.50 | 2.50 | 1.00 |
| cycles | 6.00 | 6.00 | 6.00 | 6.00 | 0.00 | 2.50 | 2.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 5.50 |
| Dispatch | 6.00 |
| Overall L1 | 6.00 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 50% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 50% |
| all | 50% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 50% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENDBR64 | N/A | |||||||||||
| VMOVUPS 0xbdc4(%RIP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbffc(%RIP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbd74(%RIP),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFMADD213PS %YMM1,%YMM0,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VSUBPS %YMM1,%YMM3,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VANDPS 0xc023(%RIP),%YMM0,%YMM4 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VPCMPGTD 0xc05b(%RIP),%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVMSKPS %YMM4,%EAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | vect (50.0%) |
| VPSLLD $0x17,%YMM3,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbdca(%RIP),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFNMADD213PS %YMM0,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFNMADD231PS 0xbdfc(%RIP),%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf73(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf2a(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbee1(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe98(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe4f(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VPADDD %YMM2,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JNE 40693e <__svml_expf8_l9+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VMOVAPS %YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 1.31% of application time for run run_0
| Source file and lines | |
| Module | attention-icx-skl256 |
| nb instructions | 50 |
| nb uops | 52 |
| loop length | 255 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 13.00 cycles |
| front end | 13.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.17 | 7.83 | 9.50 | 9.50 | 6.00 | 8.00 | 7.00 | 7.00 |
| cycles | 8.17 | 7.83 | 9.50 | 9.50 | 6.00 | 8.00 | 7.00 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 13.00 |
| Dispatch | 9.50 |
| Overall L1 | 13.00 |
| all | 50% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 40% |
| all | 96% |
| load | 93% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 90% |
| all | 87% |
| load | 93% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 73% |
| all | 29% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 48% |
| load | 47% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 45% |
| all | 44% |
| load | 47% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 38% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENDBR64 | N/A | |||||||||||
| VMOVUPS 0xbdc4(%RIP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbffc(%RIP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbd74(%RIP),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFMADD213PS %YMM1,%YMM0,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VSUBPS %YMM1,%YMM3,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VANDPS 0xc023(%RIP),%YMM0,%YMM4 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VPCMPGTD 0xc05b(%RIP),%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVMSKPS %YMM4,%EAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | vect (50.0%) |
| VPSLLD $0x17,%YMM3,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbdca(%RIP),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFNMADD213PS %YMM0,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFNMADD231PS 0xbdfc(%RIP),%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf73(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf2a(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbee1(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe98(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe4f(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VPADDD %YMM2,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | scal (6.3%) |
| JNE 40693e <__svml_expf8_l9+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| MOVZX %AL,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VMOVUPS 0xc037(%RIP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VBROADCASTSS 0x76ce(%RIP),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | scal (6.3%) |
| VCMPPS $0x1,%YMM0,%YMM2,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 | vect (50.0%) |
| VCMPPS $0x1,0xc05a(%RIP),%YMM0,%YMM3 | 2 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VANDNPS %YMM1,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VORPS %YMM2,%YMM3,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VMOVMSKPS %YMM2,%ECX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | vect (50.0%) |
| ANDN %EAX,%ECX,%EDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JE 406939 <__svml_expf8_l9+0x89> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | N/A |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | N/A |
| PUSH %RSI | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | N/A |
| PUSH %RDI | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | N/A |
| AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| SUB $0x80,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| VMOVUPS %YMM0,0x40(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | vect (50.0%) |
| VMOVUPS %YMM1,(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 | vect (50.0%) |
| LEA 0x40(%RSP),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| MOV %RSP,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | scal (12.5%) |
| CALL 4069c0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper> | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 | N/A |
| VMOVUPS (%RSP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| LEA -0x10(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | N/A |
| POP %RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| POP %RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVAPS %YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 | N/A |
The code analyzed by CQA in that panel excludes loops and represents 1.31% of application time for run run_0
| Source file and lines | |
| Module | attention-icx-skl256 |
| nb instructions | 34 |
| nb uops | 34 |
| loop length | 201 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 8.50 cycles |
| front end | 8.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 7.50 | 7.50 | 7.50 | 7.50 | 0.00 | 6.00 | 4.00 | 1.00 |
| cycles | 7.50 | 7.50 | 7.50 | 7.50 | 0.00 | 6.00 | 4.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 8.50 |
| Dispatch | 7.50 |
| Overall L1 | 8.50 |
| all | 75% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 66% |
| all | 95% |
| load | 92% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 90% |
| all | 92% |
| load | 93% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 84% |
| all | 39% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 35% |
| all | 48% |
| load | 46% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 45% |
| all | 46% |
| load | 47% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 43% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ENDBR64 | N/A | |||||||||||
| VMOVUPS 0xbdc4(%RIP),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbffc(%RIP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbd74(%RIP),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFMADD213PS %YMM1,%YMM0,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VSUBPS %YMM1,%YMM3,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VANDPS 0xc023(%RIP),%YMM0,%YMM4 | 1 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0.33 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VPCMPGTD 0xc05b(%RIP),%YMM4,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVMSKPS %YMM4,%EAX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | vect (50.0%) |
| VPSLLD $0x17,%YMM3,%YMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (50.0%) |
| VMOVUPS 0xbdca(%RIP),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VFNMADD213PS %YMM0,%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFNMADD231PS 0xbdfc(%RIP),%YMM1,%YMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf73(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbf2a(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbee1(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe98(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VFMADD213PS 0xbe4f(%RIP),%YMM4,%YMM2 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VPADDD %YMM2,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| TEST %EAX,%EAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 | N/A |
| JNE 40693e <__svml_expf8_l9+0x8e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| VMOVAPS %YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | vect (50.0%) |
| RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 | N/A |
| MOVZX %AL,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| VMOVUPS 0xc037(%RIP),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 | vect (50.0%) |
| VBROADCASTSS 0x76ce(%RIP),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 | scal (6.3%) |
| VCMPPS $0x1,%YMM0,%YMM2,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1 | 2 | 0.67 | 0.67 | 0 | 0 | 0 | 0.67 | 0 | 0 | 1-2 | 1 | vect (50.0%) |
| VCMPPS $0x1,0xc05a(%RIP),%YMM0,%YMM3 | 2 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (50.0%) |
| VANDNPS %YMM1,%YMM3,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VORPS %YMM2,%YMM3,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VMOVMSKPS %YMM2,%ECX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | vect (50.0%) |
| ANDN %EAX,%ECX,%EDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| JE 406939 <__svml_expf8_l9+0x89> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 | N/A |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ○__svml_expf8_l9 | 1.31 | 0.27 |
