OV - attention-clang-skl512 - Loop 79 - attention-clang-skl512

	Loop Id: 79	Module: attention-clang-skl512	Source: random.tcc:404-409	Coverage: 0.02%

0x3000 VMOVDQA64	%ZMM0,%ZMM1

0x3006 VMOVDQU64	0x3f8(%RSP,%RCX,8),%ZMM2    [1]

0x3011 VMOVDQU64	0x438(%RSP,%RCX,8),%ZMM3    [1]

0x301c VMOVDQU64	0x478(%RSP,%RCX,8),%ZMM4    [1]

0x3027 VMOVDQU64	0x4b8(%RSP,%RCX,8),%ZMM0    [1]

0x3032 VALIGNQ	$0x7,%ZMM1,%ZMM2,%ZMM1

0x3039 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM5

0x3040 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM6

0x3047 VALIGNQ	$0x7,%ZMM4,%ZMM0,%ZMM7

0x304e VPANDQ	%ZMM13,%ZMM2,%ZMM8

0x3054 VPANDQ	%ZMM13,%ZMM3,%ZMM9

0x305a VPANDQ	%ZMM13,%ZMM4,%ZMM10

0x3060 VPANDQ	%ZMM13,%ZMM0,%ZMM11

0x3066 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM1,%ZMM8

0x306d VPTERNLOGQ	$-0x8,%ZMM12,%ZMM5,%ZMM9

0x3074 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM6,%ZMM10

0x307b VPTERNLOGQ	$-0x8,%ZMM12,%ZMM7,%ZMM11

0x3082 VPSRLQ	$0x1,%ZMM8,%ZMM1

0x3089 VPSRLQ	$0x1,%ZMM9,%ZMM5

0x3090 VPSRLQ	$0x1,%ZMM10,%ZMM6

0x3097 VPSRLQ	$0x1,%ZMM11,%ZMM7

0x309e VPXORQ	0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1    [1]

0x30a9 VPXORQ	0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5    [1]

0x30b4 VPXORQ	0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6    [1]

0x30bf VPXORQ	0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7    [1]

0x30ca VPTESTMQ	%ZMM14,%ZMM2,%K1

0x30d0 VPTESTMQ	%ZMM14,%ZMM3,%K2

0x30d6 VPTESTMQ	%ZMM14,%ZMM4,%K3

0x30dc VPTESTMQ	%ZMM14,%ZMM0,%K4

0x30e2 VPXORQ	%ZMM15,%ZMM1,%ZMM1{%K1}

0x30e8 VPXORQ	%ZMM15,%ZMM5,%ZMM5{%K2}

0x30ee VPXORQ	%ZMM15,%ZMM6,%ZMM6{%K3}

0x30f4 VPXORQ	%ZMM15,%ZMM7,%ZMM7{%K4}

0x30fa VMOVDQU64	%ZMM1,0x3f0(%RSP,%RCX,8)    [1]

0x3105 VMOVDQU64	%ZMM5,0x430(%RSP,%RCX,8)    [1]

0x3110 VMOVDQU64	%ZMM6,0x470(%RSP,%RCX,8)    [1]

0x311b VMOVDQU64	%ZMM7,0x4b0(%RSP,%RCX,8)    [1]

0x3126 ADD	$0x20,%RCX

0x312a CMP	$0xe0,%RCX

0x3131 JNE	3000

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 409

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P0, P5,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	10.75
P0 cycles	14.00
P1 cycles	1.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	14.00
P6 cycles	1.00
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.86
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P0, P5,
Function	main
Source	random.tcc:404-409
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	10.75
P0 cycles	14.00
P1 cycles	1.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	14.00
P6 cycles	1.00
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	8.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.86
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:404-409
Module	attention-clang-skl512

The loop is defined in /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	40
nb uops	39
loop length	311
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.00	1.00	4.00	4.00	4.00	14.00	1.00	4.00
cycles	14.00	1.00	4.00	4.00	4.00	14.00	1.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.75
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

28% of peak load performance is reached (36.57 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (18.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA64 %ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQU64 0x3f8(%RSP,%RCX,8),%ZMM2	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x438(%RSP,%RCX,8),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x478(%RSP,%RCX,8),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x4b8(%RSP,%RCX,8),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VALIGNQ $0x7,%ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM5	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM6	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM4,%ZMM0,%ZMM7	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPANDQ %ZMM13,%ZMM2,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM3,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM4,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM1,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM5,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM6,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM7,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPSRLQ $0x1,%ZMM8,%ZMM1	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM9,%ZMM5	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM10,%ZMM6	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM11,%ZMM7	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPXORQ 0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM2,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM3,%K2	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM4,%K3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM0,%K4	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPXORQ %ZMM15,%ZMM1,%ZMM1{%K1}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM5,%ZMM5{%K2}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM6,%ZMM6{%K3}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM7,%ZMM7{%K4}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VMOVDQU64 %ZMM1,0x3f0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM5,0x430(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM6,0x470(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM7,0x4b0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
ADD $0x20,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0xe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 3000 <main+0xa60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	random.tcc:404-409
Module	attention-clang-skl512

The loop is defined in /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-409.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 512 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	40
nb uops	39
loop length	311
used x86 registers	2
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	14.00	1.00	4.00	4.00	4.00	14.00	1.00	4.00
cycles	14.00	1.00	4.00	4.00	4.00	14.00	1.00	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.75
Dispatch	14.00
Data deps.	1.00
Overall L1	14.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

28% of peak load performance is reached (36.57 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (18.29 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VMOVDQA64 %ZMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0.25	vect (100.0%)
VMOVDQU64 0x3f8(%RSP,%RCX,8),%ZMM2	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x438(%RSP,%RCX,8),%ZMM3	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x478(%RSP,%RCX,8),%ZMM4	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VMOVDQU64 0x4b8(%RSP,%RCX,8),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	5	0.50	vect (100.0%)
VALIGNQ $0x7,%ZMM1,%ZMM2,%ZMM1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM5	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM6	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VALIGNQ $0x7,%ZMM4,%ZMM0,%ZMM7	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPANDQ %ZMM13,%ZMM2,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM3,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM4,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPANDQ %ZMM13,%ZMM0,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM1,%ZMM8	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM5,%ZMM9	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM6,%ZMM10	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPTERNLOGQ $-0x8,%ZMM12,%ZMM7,%ZMM11	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPSRLQ $0x1,%ZMM8,%ZMM1	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM9,%ZMM5	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM10,%ZMM6	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPSRLQ $0x1,%ZMM11,%ZMM7	1	1	0	0	0	0	0	0	0	1	1	vect (100.0%)
VPXORQ 0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ 0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7	1	0.50	0	0.50	0.50	0	0.50	0	0	1	0.50	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM2,%K1	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM3,%K2	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM4,%K3	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPTESTMQ %ZMM14,%ZMM0,%K4	1	0	0	0	0	0	1	0	0	3	1	vect (100.0%)
VPXORQ %ZMM15,%ZMM1,%ZMM1{%K1}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM5,%ZMM5{%K2}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM6,%ZMM6{%K3}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VPXORQ %ZMM15,%ZMM7,%ZMM7{%K4}	1	0.50	0	0	0	0	0.50	0	0	1	0.50	vect (100.0%)
VMOVDQU64 %ZMM1,0x3f0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM5,0x430(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM6,0x470(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
VMOVDQU64 %ZMM7,0x4b0(%RSP,%RCX,8)	1	0	0	0.33	0.33	1	0	0	0.33	4	1	vect (100.0%)
ADD $0x20,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP $0xe0,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JNE 3000 <main+0xa60>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code