OV - attention-clang-skl512 - Loop 78 - attention-clang-skl512

	Loop Id: 78	Module: attention-clang-skl512	Source: attention_v2.cpp:163-163 [...]	Coverage: 0.97%

0x2f60 MOV	%RCX,%RDX

0x2f63 INC	%RCX

0x2f66 MOV	%RCX,0x1770(%RSP)

0x2f6e MOV	0x3f0(%RSP,%RDX,8),%RDX

0x2f76 MOV	%RDX,%RSI

0x2f79 SHR	$0xb,%RSI

0x2f7d MOV	%ESI,%ESI

0x2f7f XOR	%RDX,%RSI

0x2f82 MOV	%ESI,%EDX

0x2f84 SAL	$0x7,%EDX

0x2f87 AND	$-0x62d3a980,%EDX

0x2f8d XOR	%RSI,%RDX

0x2f90 MOV	%EDX,%ESI

0x2f92 SAL	$0xf,%ESI

0x2f95 AND	$-0x103a0000,%ESI

0x2f9b XOR	%RDX,%RSI

0x2f9e MOV	%RSI,%RDX

0x2fa1 SHR	$0x12,%RDX

0x2fa5 XOR	%ESI,%EDX

0x2fa7 VCVTUSI2SS	%EDX,%XMM15,%XMM0

0x2fad VMULSS	0x3053(%RIP),%XMM0,%XMM0

0x2fb5 VUCOMISS	0x304f(%RIP),%XMM0

0x2fbd JB	3345

0x2fc3 CMP	$0x270,%RCX

0x2fca JB	2f60

0x2fcc VPBROADCASTQ	0x3f0(%RSP),%ZMM0

0x2fd4 XOR	%ECX,%ECX

0x2fd6 VPBROADCASTQ	0x3058(%RIP),%ZMM12

0x2fe0 VPBROADCASTQ	0x3056(%RIP),%ZMM13

0x2fea VPBROADCASTQ	0x3054(%RIP),%ZMM14

0x2ff4 VPBROADCASTQ	0x3052(%RIP),%ZMM15

0x2ffe XCHG	%AX,%AX

  (79) 0x3000 VMOVDQA64	%ZMM0,%ZMM1

  (79) 0x3006 VMOVDQU64	0x3f8(%RSP,%RCX,8),%ZMM2

  (79) 0x3011 VMOVDQU64	0x438(%RSP,%RCX,8),%ZMM3

  (79) 0x301c VMOVDQU64	0x478(%RSP,%RCX,8),%ZMM4

  (79) 0x3027 VMOVDQU64	0x4b8(%RSP,%RCX,8),%ZMM0

  (79) 0x3032 VALIGNQ	$0x7,%ZMM1,%ZMM2,%ZMM1

  (79) 0x3039 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM5

  (79) 0x3040 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM6

  (79) 0x3047 VALIGNQ	$0x7,%ZMM4,%ZMM0,%ZMM7

  (79) 0x304e VPANDQ	%ZMM13,%ZMM2,%ZMM8

  (79) 0x3054 VPANDQ	%ZMM13,%ZMM3,%ZMM9

  (79) 0x305a VPANDQ	%ZMM13,%ZMM4,%ZMM10

  (79) 0x3060 VPANDQ	%ZMM13,%ZMM0,%ZMM11

  (79) 0x3066 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM1,%ZMM8

  (79) 0x306d VPTERNLOGQ	$-0x8,%ZMM12,%ZMM5,%ZMM9

  (79) 0x3074 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM6,%ZMM10

  (79) 0x307b VPTERNLOGQ	$-0x8,%ZMM12,%ZMM7,%ZMM11

  (79) 0x3082 VPSRLQ	$0x1,%ZMM8,%ZMM1

  (79) 0x3089 VPSRLQ	$0x1,%ZMM9,%ZMM5

  (79) 0x3090 VPSRLQ	$0x1,%ZMM10,%ZMM6

  (79) 0x3097 VPSRLQ	$0x1,%ZMM11,%ZMM7

  (79) 0x309e VPXORQ	0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1

  (79) 0x30a9 VPXORQ	0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5

  (79) 0x30b4 VPXORQ	0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6

  (79) 0x30bf VPXORQ	0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7

  (79) 0x30ca VPTESTMQ	%ZMM14,%ZMM2,%K1

  (79) 0x30d0 VPTESTMQ	%ZMM14,%ZMM3,%K2

  (79) 0x30d6 VPTESTMQ	%ZMM14,%ZMM4,%K3

  (79) 0x30dc VPTESTMQ	%ZMM14,%ZMM0,%K4

  (79) 0x30e2 VPXORQ	%ZMM15,%ZMM1,%ZMM1{%K1}

  (79) 0x30e8 VPXORQ	%ZMM15,%ZMM5,%ZMM5{%K2}

  (79) 0x30ee VPXORQ	%ZMM15,%ZMM6,%ZMM6{%K3}

  (79) 0x30f4 VPXORQ	%ZMM15,%ZMM7,%ZMM7{%K4}

  (79) 0x30fa VMOVDQU64	%ZMM1,0x3f0(%RSP,%RCX,8)

  (79) 0x3105 VMOVDQU64	%ZMM5,0x430(%RSP,%RCX,8)

  (79) 0x3110 VMOVDQU64	%ZMM6,0x470(%RSP,%RCX,8)

  (79) 0x311b VMOVDQU64	%ZMM7,0x4b0(%RSP,%RCX,8)

  (79) 0x3126 ADD	$0x20,%RCX

  (79) 0x312a CMP	$0xe0,%RCX

  (79) 0x3131 JNE	3000

0x3137 VEXTRACTI32X4	$0x3,%ZMM0,%XMM0

0x313e VPEXTRQ	$0x1,%XMM0,%RSI

0x3144 AND	$-0x80000000,%RSI

0x314b MOV	0xaf8(%RSP),%RDX

0x3153 MOV	0xb00(%RSP),%RCX

0x315b MOV	%EDX,%EDI

0x315d AND	$0x7ffffffe,%EDI

0x3163 OR	%RSI,%RDI

0x3166 SHR	$0x1,%RDI

0x3169 XOR	0x1758(%RSP),%RDI

0x3171 MOV	%EDX,%ESI

0x3173 AND	$0x1,%ESI

0x3176 NEG	%ESI

0x3178 MOV	$-0x66f74f21,%R8D

0x317e AND	%R8D,%ESI

0x3181 XOR	%RDI,%RSI

0x3184 MOV	%RSI,0xaf0(%RSP)

0x318c AND	$-0x80000000,%RDX

0x3193 MOV	%ECX,%ESI

0x3195 AND	$0x7ffffffe,%ESI

0x319b OR	%RDX,%RSI

0x319e SHR	$0x1,%RSI

0x31a1 XOR	0x1760(%RSP),%RSI

0x31a9 MOV	%ECX,%EDX

0x31ab AND	$0x1,%EDX

0x31ae NEG	%EDX

0x31b0 AND	%R8D,%EDX

0x31b3 XOR	%RSI,%RDX

0x31b6 MOV	%RDX,0xaf8(%RSP)

0x31be AND	$-0x80000000,%RCX

0x31c5 MOV	0xb08(%RSP),%RDX

0x31cd MOV	%EDX,%ESI

0x31cf VPBROADCASTQ	%RDX,%XMM0

0x31d5 AND	$0x7ffffffe,%EDX

0x31db OR	%RCX,%RDX

0x31de SHR	$0x1,%RDX

0x31e1 XOR	0x1768(%RSP),%RDX

0x31e9 AND	$0x1,%ESI

0x31ec NEG	%ESI

0x31ee MOV	$-0x66f74f21,%EDI

0x31f3 AND	%R8D,%ESI

0x31f6 XOR	%RDX,%RSI

0x31f9 MOV	%RSI,0xb00(%RSP)

0x3201 MOV	$0xe8,%ECX

0x3206 VPBROADCASTQ	0x2e29(%RIP),%XMM5

0x320f VPBROADCASTQ	0x2e28(%RIP),%XMM6

0x3218 VPBROADCASTQ	0x2e27(%RIP),%XMM7

0x3221 VPBROADCASTQ	0x2e26(%RIP),%XMM8

0x322a NOPW	(%RAX,%RAX,1)

  (80) 0x3230 VMOVDQU	0x3d0(%RSP,%RCX,8),%XMM1

  (80) 0x3239 VMOVDQU	0x3e0(%RSP,%RCX,8),%XMM2

  (80) 0x3242 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (80) 0x3248 VMOVDQU	0x3f0(%RSP,%RCX,8),%XMM3

  (80) 0x3251 VPAND	%XMM6,%XMM1,%XMM4

  (80) 0x3255 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM4

  (80) 0x325c VPSRLQ	$0x1,%XMM4,%XMM0

  (80) 0x3261 VPXOR	-0x350(%RSP,%RCX,8),%XMM0,%XMM0

  (80) 0x326a VPTESTMQ	%XMM7,%XMM1,%K1

  (80) 0x3270 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (80) 0x3276 VMOVDQU	%XMM0,0x3c8(%RSP,%RCX,8)

  (80) 0x327f VPALIGNR	$0x8,%XMM1,%XMM2,%XMM0

  (80) 0x3285 VPAND	%XMM6,%XMM2,%XMM1

  (80) 0x3289 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

  (80) 0x3290 VPSRLQ	$0x1,%XMM1,%XMM0

  (80) 0x3295 VPXOR	-0x340(%RSP,%RCX,8),%XMM0,%XMM0

  (80) 0x329e VPTESTMQ	%XMM7,%XMM2,%K1

  (80) 0x32a4 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (80) 0x32aa VMOVDQU	%XMM0,0x3d8(%RSP,%RCX,8)

  (80) 0x32b3 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM0

  (80) 0x32b9 VPAND	%XMM6,%XMM3,%XMM1

  (80) 0x32bd VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

  (80) 0x32c4 VPSRLQ	$0x1,%XMM1,%XMM0

  (80) 0x32c9 VPXOR	-0x330(%RSP,%RCX,8),%XMM0,%XMM0

  (80) 0x32d2 VPTESTMQ	%XMM7,%XMM3,%K1

  (80) 0x32d8 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (80) 0x32de VMOVDQU	%XMM0,0x3e8(%RSP,%RCX,8)

  (80) 0x32e7 ADD	$0x6,%RCX

  (80) 0x32eb VMOVDQA	%XMM3,%XMM0

  (80) 0x32ef CMP	$0x274,%RCX

  (80) 0x32f6 JNE	3230

0x32fc MOV	0x1768(%RSP),%RCX

0x3304 MOV	$-0x80000000,%RDX

0x330b AND	%RDX,%RCX

0x330e MOV	0x3f0(%RSP),%RDX

0x3316 MOV	%EDX,%ESI

0x3318 AND	$0x7ffffffe,%ESI

0x331e OR	%RCX,%RSI

0x3321 SHR	$0x1,%RSI

0x3324 XOR	0x1050(%RSP),%RSI

0x332c AND	$0x1,%EDX

0x332f NEG	%EDX

0x3331 AND	%EDI,%EDX

0x3333 XOR	%RSI,%RDX

0x3336 MOV	%RDX,0x1768(%RSP)

0x333e XOR	%ECX,%ECX

0x3340 JMP	2f60

0x3345 VMOVSS	%XMM0,(%R14,%RAX,4)

0x334b INC	%RAX

0x334e CMP	0x68(%RSP),%RAX

0x3353 JNE	2fc3

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 163 - 163

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.91
CQA speedup if FP arith vectorized	2.08
CQA speedup if fully vectorized	12.24
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.56
Bottlenecks
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.63
CQA cycles if no scalar integer	4.25
CQA cycles if FP arith vectorized	7.99
CQA cycles if fully vectorized	1.36
Front-end cycles	16.63
P0 cycles	10.63
P1 cycles	10.63
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	4.00
P5 cycles	10.63
P6 cycles	10.63
P7 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	66.50
Nb loads	13.00
Nb stores	4.00
Nb stack references	6.50
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.52
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	28.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.76
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.89
Vector-efficiency ratio all	9.65
Vector-efficiency ratio load	8.98
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.51

Metric	Value
CQA speedup if no scalar integer	4.29
CQA speedup if FP arith vectorized	1.95
CQA speedup if fully vectorized	11.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.75
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	13.20
CQA cycles if fully vectorized	2.18
Front-end cycles	25.75
P0 cycles	16.25
P1 cycles	16.25
P2 cycles	11.00
P3 cycles	11.00
P4 cycles	6.00
P5 cycles	16.25
P6 cycles	16.25
P7 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	103.00
Nb loads	22.00
Nb stores	6.00
Nb stack references	11.00
FLOP/cycle	0.04
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.23
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	44.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	1.52
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	1.79
Vector-efficiency ratio all	10.13
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	11.46
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.93

Metric	Value
CQA speedup if no scalar integer	3.00
CQA speedup if FP arith vectorized	2.71
CQA speedup if fully vectorized	14.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.77
CQA cycles if fully vectorized	0.53
Front-end cycles	7.50
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	30.00
Nb loads	4.00
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	0.13
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.17
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.09

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-clang-skl512

The loop is defined in:

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.63 to 1.36 cycles (12.24x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPEXTRQ: 0 occurrences
VUCOMISS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 96 bytes (24 single precision FP elements). The binary loop is storing 28 bytes (7 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	66.50
loop length	315
used x86 registers	7
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	2.50
nb stack references	6.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	10.63	10.63	6.50	6.50	4.00	10.63	10.63	4.00
cycles	10.63	10.63	6.50	6.50	4.00	10.63	10.63	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	16.63
Dispatch	10.63
Data deps.	1.00
Overall L1	16.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	8%
store	10%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.63 cycles. At this rate:

3% of peak load performance is reached (4.86 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.65 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-clang-skl512

The loop is defined in:

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.75 to 6.00 cycles (4.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 25.75 to 2.18 cycles (11.80x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VPEXTRQ: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404
VUCOMISS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3558

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 168 bytes (42 single precision FP elements). The binary loop is storing 44 bytes (11 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	103
loop length	502
used x86 registers	8
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	5
nb stack references	11

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	25.75 cycles
front end	25.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	16.25	16.25	11.00	11.00	6.00	16.25	16.25	6.00
cycles	16.25	16.25	11.00	11.00	6.00	16.25	16.25	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	25.75
Dispatch	16.25
Data deps.	1.00
Overall L1	25.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	11%
store	11%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.75 cycles. At this rate:

5% of peak load performance is reached (6.52 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.71 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.75 to 16.25 cycles (1.58x speedup).

ASM code

In the binary file, the address of the loop is: 2fc3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RCX,0x1770(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x3f0(%RSP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR %ESI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x3053(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS 0x304f(%RIP),%XMM0	2	1	0	0.50	0.50	0	0	0	0	3	1	scal (6.3%)
JB 3345 <main+0xda5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 2f60 <main+0x9c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0x3f0(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ 0x3058(%RIP),%ZMM12	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x3056(%RIP),%ZMM13	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x3054(%RIP),%ZMM14	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x3052(%RIP),%ZMM15	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTI32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPEXTRQ $0x1,%XMM0,%RSI	2	1	0	0	0	0	1	0	0	3	1	scal (12.5%)
AND $-0x80000000,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xaf8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xb00(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1758(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xaf0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1760(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %R8D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0xaf8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb08(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
AND $0x7ffffffe,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
OR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR 0x1768(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xb00(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0xe8,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VPBROADCASTQ 0x2e29(%RIP),%XMM5	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x2e28(%RIP),%XMM6	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x2e27(%RIP),%XMM7	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x2e26(%RIP),%XMM8	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1768(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RDX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RCX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1050(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %EDI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0x1768(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 2f60 <main+0x9c0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%R14,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x68(%RSP),%RAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 2fc3 <main+0xa23>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-clang-skl512

The loop is defined in:

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:163

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.50 to 2.50 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.50 to 0.53 cycles (14.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VUCOMISS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3558

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 24 bytes (6 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	29
nb uops	30
loop length	128
used x86 registers	6
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.00	5.00	2.00	2.00	2.00	5.00	5.00	2.00
cycles	5.00	5.00	2.00	2.00	2.00	5.00	5.00	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.50
Dispatch	5.00
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	9%
load	6%
store	9%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

2% of peak load performance is reached (3.20 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 2fc3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RCX,0x1770(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x3f0(%RSP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR %ESI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x3053(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS 0x304f(%RIP),%XMM0	2	1	0	0.50	0.50	0	0	0	0	3	1	scal (6.3%)
JB 3345 <main+0xda5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 2f60 <main+0x9c0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VMOVSS %XMM0,(%R14,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x68(%RSP),%RAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 2fc3 <main+0xa23>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code