OV - attention-clang-skl512 - Loop 69 - attention-clang-skl512

	Loop Id: 69	Module: attention-clang-skl512	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.12%

0x3390 MOV	%RCX,%RDX

0x3393 INC	%RCX

0x3396 MOV	%RCX,0x1770(%RSP)

0x339e MOV	0x3f0(%RSP,%RDX,8),%RDX

0x33a6 MOV	%RDX,%RSI

0x33a9 SHR	$0xb,%RSI

0x33ad MOV	%ESI,%ESI

0x33af XOR	%RDX,%RSI

0x33b2 MOV	%ESI,%EDX

0x33b4 SAL	$0x7,%EDX

0x33b7 AND	$-0x62d3a980,%EDX

0x33bd XOR	%RSI,%RDX

0x33c0 MOV	%EDX,%ESI

0x33c2 SAL	$0xf,%ESI

0x33c5 AND	$-0x103a0000,%ESI

0x33cb XOR	%RDX,%RSI

0x33ce MOV	%RSI,%RDX

0x33d1 SHR	$0x12,%RDX

0x33d5 XOR	%ESI,%EDX

0x33d7 VCVTUSI2SS	%EDX,%XMM15,%XMM0

0x33dd VMULSS	0x2c23(%RIP),%XMM0,%XMM0

0x33e5 VUCOMISS	0x2c1f(%RIP),%XMM0

0x33ed JB	3775

0x33f3 CMP	$0x270,%RCX

0x33fa JB	3390

0x33fc VPBROADCASTQ	0x3f0(%RSP),%ZMM0

0x3404 XOR	%ECX,%ECX

0x3406 VPBROADCASTQ	0x2c28(%RIP),%ZMM12

0x3410 VPBROADCASTQ	0x2c26(%RIP),%ZMM13

0x341a VPBROADCASTQ	0x2c24(%RIP),%ZMM14

0x3424 VPBROADCASTQ	0x2c22(%RIP),%ZMM15

0x342e XCHG	%AX,%AX

  (76) 0x3430 VMOVDQA64	%ZMM0,%ZMM1

  (76) 0x3436 VMOVDQU64	0x3f8(%RSP,%RCX,8),%ZMM2

  (76) 0x3441 VMOVDQU64	0x438(%RSP,%RCX,8),%ZMM3

  (76) 0x344c VMOVDQU64	0x478(%RSP,%RCX,8),%ZMM4

  (76) 0x3457 VMOVDQU64	0x4b8(%RSP,%RCX,8),%ZMM0

  (76) 0x3462 VALIGNQ	$0x7,%ZMM1,%ZMM2,%ZMM1

  (76) 0x3469 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM5

  (76) 0x3470 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM6

  (76) 0x3477 VALIGNQ	$0x7,%ZMM4,%ZMM0,%ZMM7

  (76) 0x347e VPANDQ	%ZMM13,%ZMM2,%ZMM8

  (76) 0x3484 VPANDQ	%ZMM13,%ZMM3,%ZMM9

  (76) 0x348a VPANDQ	%ZMM13,%ZMM4,%ZMM10

  (76) 0x3490 VPANDQ	%ZMM13,%ZMM0,%ZMM11

  (76) 0x3496 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM1,%ZMM8

  (76) 0x349d VPTERNLOGQ	$-0x8,%ZMM12,%ZMM5,%ZMM9

  (76) 0x34a4 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM6,%ZMM10

  (76) 0x34ab VPTERNLOGQ	$-0x8,%ZMM12,%ZMM7,%ZMM11

  (76) 0x34b2 VPSRLQ	$0x1,%ZMM8,%ZMM1

  (76) 0x34b9 VPSRLQ	$0x1,%ZMM9,%ZMM5

  (76) 0x34c0 VPSRLQ	$0x1,%ZMM10,%ZMM6

  (76) 0x34c7 VPSRLQ	$0x1,%ZMM11,%ZMM7

  (76) 0x34ce VPXORQ	0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1

  (76) 0x34d9 VPXORQ	0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5

  (76) 0x34e4 VPXORQ	0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6

  (76) 0x34ef VPXORQ	0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7

  (76) 0x34fa VPTESTMQ	%ZMM14,%ZMM2,%K1

  (76) 0x3500 VPTESTMQ	%ZMM14,%ZMM3,%K2

  (76) 0x3506 VPTESTMQ	%ZMM14,%ZMM4,%K3

  (76) 0x350c VPTESTMQ	%ZMM14,%ZMM0,%K4

  (76) 0x3512 VPXORQ	%ZMM15,%ZMM1,%ZMM1{%K1}

  (76) 0x3518 VPXORQ	%ZMM15,%ZMM5,%ZMM5{%K2}

  (76) 0x351e VPXORQ	%ZMM15,%ZMM6,%ZMM6{%K3}

  (76) 0x3524 VPXORQ	%ZMM15,%ZMM7,%ZMM7{%K4}

  (76) 0x352a VMOVDQU64	%ZMM1,0x3f0(%RSP,%RCX,8)

  (76) 0x3535 VMOVDQU64	%ZMM5,0x430(%RSP,%RCX,8)

  (76) 0x3540 VMOVDQU64	%ZMM6,0x470(%RSP,%RCX,8)

  (76) 0x354b VMOVDQU64	%ZMM7,0x4b0(%RSP,%RCX,8)

  (76) 0x3556 ADD	$0x20,%RCX

  (76) 0x355a CMP	$0xe0,%RCX

  (76) 0x3561 JNE	3430

0x3567 VEXTRACTI32X4	$0x3,%ZMM0,%XMM0

0x356e VPEXTRQ	$0x1,%XMM0,%RSI

0x3574 AND	$-0x80000000,%RSI

0x357b MOV	0xaf8(%RSP),%RDX

0x3583 MOV	0xb00(%RSP),%RCX

0x358b MOV	%EDX,%EDI

0x358d AND	$0x7ffffffe,%EDI

0x3593 OR	%RSI,%RDI

0x3596 SHR	$0x1,%RDI

0x3599 XOR	0x1758(%RSP),%RDI

0x35a1 MOV	%EDX,%ESI

0x35a3 AND	$0x1,%ESI

0x35a6 NEG	%ESI

0x35a8 MOV	$-0x66f74f21,%R8D

0x35ae AND	%R8D,%ESI

0x35b1 XOR	%RDI,%RSI

0x35b4 MOV	%RSI,0xaf0(%RSP)

0x35bc AND	$-0x80000000,%RDX

0x35c3 MOV	%ECX,%ESI

0x35c5 AND	$0x7ffffffe,%ESI

0x35cb OR	%RDX,%RSI

0x35ce SHR	$0x1,%RSI

0x35d1 XOR	0x1760(%RSP),%RSI

0x35d9 MOV	%ECX,%EDX

0x35db AND	$0x1,%EDX

0x35de NEG	%EDX

0x35e0 AND	%R8D,%EDX

0x35e3 XOR	%RSI,%RDX

0x35e6 MOV	%RDX,0xaf8(%RSP)

0x35ee AND	$-0x80000000,%RCX

0x35f5 MOV	0xb08(%RSP),%RDX

0x35fd MOV	%EDX,%ESI

0x35ff VPBROADCASTQ	%RDX,%XMM0

0x3605 AND	$0x7ffffffe,%EDX

0x360b OR	%RCX,%RDX

0x360e SHR	$0x1,%RDX

0x3611 XOR	0x1768(%RSP),%RDX

0x3619 AND	$0x1,%ESI

0x361c NEG	%ESI

0x361e MOV	$-0x66f74f21,%EDI

0x3623 AND	%R8D,%ESI

0x3626 XOR	%RDX,%RSI

0x3629 MOV	%RSI,0xb00(%RSP)

0x3631 MOV	$0xe8,%ECX

0x3636 VPBROADCASTQ	0x29f9(%RIP),%XMM5

0x363f VPBROADCASTQ	0x29f8(%RIP),%XMM6

0x3648 VPBROADCASTQ	0x29f7(%RIP),%XMM7

0x3651 VPBROADCASTQ	0x29f6(%RIP),%XMM8

0x365a NOPW	(%RAX,%RAX,1)

  (77) 0x3660 VMOVDQU	0x3d0(%RSP,%RCX,8),%XMM1

  (77) 0x3669 VMOVDQU	0x3e0(%RSP,%RCX,8),%XMM2

  (77) 0x3672 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

  (77) 0x3678 VMOVDQU	0x3f0(%RSP,%RCX,8),%XMM3

  (77) 0x3681 VPAND	%XMM6,%XMM1,%XMM4

  (77) 0x3685 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM4

  (77) 0x368c VPSRLQ	$0x1,%XMM4,%XMM0

  (77) 0x3691 VPXOR	-0x350(%RSP,%RCX,8),%XMM0,%XMM0

  (77) 0x369a VPTESTMQ	%XMM7,%XMM1,%K1

  (77) 0x36a0 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (77) 0x36a6 VMOVDQU	%XMM0,0x3c8(%RSP,%RCX,8)

  (77) 0x36af VPALIGNR	$0x8,%XMM1,%XMM2,%XMM0

  (77) 0x36b5 VPAND	%XMM6,%XMM2,%XMM1

  (77) 0x36b9 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

  (77) 0x36c0 VPSRLQ	$0x1,%XMM1,%XMM0

  (77) 0x36c5 VPXOR	-0x340(%RSP,%RCX,8),%XMM0,%XMM0

  (77) 0x36ce VPTESTMQ	%XMM7,%XMM2,%K1

  (77) 0x36d4 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (77) 0x36da VMOVDQU	%XMM0,0x3d8(%RSP,%RCX,8)

  (77) 0x36e3 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM0

  (77) 0x36e9 VPAND	%XMM6,%XMM3,%XMM1

  (77) 0x36ed VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

  (77) 0x36f4 VPSRLQ	$0x1,%XMM1,%XMM0

  (77) 0x36f9 VPXOR	-0x330(%RSP,%RCX,8),%XMM0,%XMM0

  (77) 0x3702 VPTESTMQ	%XMM7,%XMM3,%K1

  (77) 0x3708 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

  (77) 0x370e VMOVDQU	%XMM0,0x3e8(%RSP,%RCX,8)

  (77) 0x3717 ADD	$0x6,%RCX

  (77) 0x371b VMOVDQA	%XMM3,%XMM0

  (77) 0x371f CMP	$0x274,%RCX

  (77) 0x3726 JNE	3660

0x372c MOV	0x1768(%RSP),%RCX

0x3734 MOV	$-0x80000000,%RDX

0x373b AND	%RDX,%RCX

0x373e MOV	0x3f0(%RSP),%RDX

0x3746 MOV	%EDX,%ESI

0x3748 AND	$0x7ffffffe,%ESI

0x374e OR	%RCX,%RSI

0x3751 SHR	$0x1,%RSI

0x3754 XOR	0x1050(%RSP),%RSI

0x375c AND	$0x1,%EDX

0x375f NEG	%EDX

0x3761 AND	%EDI,%EDX

0x3763 XOR	%RSI,%RDX

0x3766 MOV	%RDX,0x1768(%RSP)

0x376e XOR	%ECX,%ECX

0x3770 JMP	3390

0x3775 VMOVSS	%XMM0,(%RBX,%RAX,4)

0x377a JMP	37e3

  (73) 0x3780 MOV	%RCX,%RDX

  (73) 0x3783 INC	%RCX

  (73) 0x3786 MOV	%RCX,0x1770(%RSP)

  (73) 0x378e MOV	0x3f0(%RSP,%RDX,8),%RDX

  (73) 0x3796 MOV	%RDX,%RSI

  (73) 0x3799 SHR	$0xb,%RSI

  (73) 0x379d MOV	%ESI,%ESI

  (73) 0x379f XOR	%RDX,%RSI

  (73) 0x37a2 MOV	%ESI,%EDX

  (73) 0x37a4 SAL	$0x7,%EDX

  (73) 0x37a7 AND	$-0x62d3a980,%EDX

  (73) 0x37ad XOR	%RSI,%RDX

  (73) 0x37b0 MOV	%EDX,%ESI

  (73) 0x37b2 SAL	$0xf,%ESI

  (73) 0x37b5 AND	$-0x103a0000,%ESI

  (73) 0x37bb XOR	%RDX,%RSI

  (73) 0x37be MOV	%RSI,%RDX

  (73) 0x37c1 SHR	$0x12,%RDX

  (73) 0x37c5 XOR	%ESI,%EDX

  (73) 0x37c7 VCVTUSI2SS	%EDX,%XMM15,%XMM0

  (73) 0x37cd VMULSS	0x2833(%RIP),%XMM0,%XMM0

  (73) 0x37d5 VUCOMISS	0x282f(%RIP),%XMM0

  (73) 0x37dd JB	3b65

  (73) 0x37e3 CMP	$0x270,%RCX

  (73) 0x37ea JB	3780

  (73) 0x37ec VPBROADCASTQ	0x3f0(%RSP),%ZMM0

  (73) 0x37f4 XOR	%ECX,%ECX

  (73) 0x37f6 VPBROADCASTQ	0x2838(%RIP),%ZMM12

  (73) 0x3800 VPBROADCASTQ	0x2836(%RIP),%ZMM13

  (73) 0x380a VPBROADCASTQ	0x2834(%RIP),%ZMM14

  (73) 0x3814 VPBROADCASTQ	0x2832(%RIP),%ZMM15

  (73) 0x381e XCHG	%AX,%AX

    (74) 0x3820 VMOVDQA64	%ZMM0,%ZMM1

    (74) 0x3826 VMOVDQU64	0x3f8(%RSP,%RCX,8),%ZMM2

    (74) 0x3831 VMOVDQU64	0x438(%RSP,%RCX,8),%ZMM3

    (74) 0x383c VMOVDQU64	0x478(%RSP,%RCX,8),%ZMM4

    (74) 0x3847 VMOVDQU64	0x4b8(%RSP,%RCX,8),%ZMM0

    (74) 0x3852 VALIGNQ	$0x7,%ZMM1,%ZMM2,%ZMM1

    (74) 0x3859 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM5

    (74) 0x3860 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM6

    (74) 0x3867 VALIGNQ	$0x7,%ZMM4,%ZMM0,%ZMM7

    (74) 0x386e VPANDQ	%ZMM13,%ZMM2,%ZMM8

    (74) 0x3874 VPANDQ	%ZMM13,%ZMM3,%ZMM9

    (74) 0x387a VPANDQ	%ZMM13,%ZMM4,%ZMM10

    (74) 0x3880 VPANDQ	%ZMM13,%ZMM0,%ZMM11

    (74) 0x3886 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM1,%ZMM8

    (74) 0x388d VPTERNLOGQ	$-0x8,%ZMM12,%ZMM5,%ZMM9

    (74) 0x3894 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM6,%ZMM10

    (74) 0x389b VPTERNLOGQ	$-0x8,%ZMM12,%ZMM7,%ZMM11

    (74) 0x38a2 VPSRLQ	$0x1,%ZMM8,%ZMM1

    (74) 0x38a9 VPSRLQ	$0x1,%ZMM9,%ZMM5

    (74) 0x38b0 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (74) 0x38b7 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (74) 0x38be VPXORQ	0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1

    (74) 0x38c9 VPXORQ	0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5

    (74) 0x38d4 VPXORQ	0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6

    (74) 0x38df VPXORQ	0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7

    (74) 0x38ea VPTESTMQ	%ZMM14,%ZMM2,%K1

    (74) 0x38f0 VPTESTMQ	%ZMM14,%ZMM3,%K2

    (74) 0x38f6 VPTESTMQ	%ZMM14,%ZMM4,%K3

    (74) 0x38fc VPTESTMQ	%ZMM14,%ZMM0,%K4

    (74) 0x3902 VPXORQ	%ZMM15,%ZMM1,%ZMM1{%K1}

    (74) 0x3908 VPXORQ	%ZMM15,%ZMM5,%ZMM5{%K2}

    (74) 0x390e VPXORQ	%ZMM15,%ZMM6,%ZMM6{%K3}

    (74) 0x3914 VPXORQ	%ZMM15,%ZMM7,%ZMM7{%K4}

    (74) 0x391a VMOVDQU64	%ZMM1,0x3f0(%RSP,%RCX,8)

    (74) 0x3925 VMOVDQU64	%ZMM5,0x430(%RSP,%RCX,8)

    (74) 0x3930 VMOVDQU64	%ZMM6,0x470(%RSP,%RCX,8)

    (74) 0x393b VMOVDQU64	%ZMM7,0x4b0(%RSP,%RCX,8)

    (74) 0x3946 ADD	$0x20,%RCX

    (74) 0x394a CMP	$0xe0,%RCX

    (74) 0x3951 JNE	3820

  (73) 0x3957 VEXTRACTI32X4	$0x3,%ZMM0,%XMM0

  (73) 0x395e VPEXTRQ	$0x1,%XMM0,%RSI

  (73) 0x3964 AND	$-0x80000000,%RSI

  (73) 0x396b MOV	0xaf8(%RSP),%RDX

  (73) 0x3973 MOV	0xb00(%RSP),%RCX

  (73) 0x397b MOV	%EDX,%EDI

  (73) 0x397d AND	$0x7ffffffe,%EDI

  (73) 0x3983 OR	%RSI,%RDI

  (73) 0x3986 SHR	$0x1,%RDI

  (73) 0x3989 XOR	0x1758(%RSP),%RDI

  (73) 0x3991 MOV	%EDX,%ESI

  (73) 0x3993 AND	$0x1,%ESI

  (73) 0x3996 NEG	%ESI

  (73) 0x3998 MOV	$-0x66f74f21,%R8D

  (73) 0x399e AND	%R8D,%ESI

  (73) 0x39a1 XOR	%RDI,%RSI

  (73) 0x39a4 MOV	%RSI,0xaf0(%RSP)

  (73) 0x39ac AND	$-0x80000000,%RDX

  (73) 0x39b3 MOV	%ECX,%ESI

  (73) 0x39b5 AND	$0x7ffffffe,%ESI

  (73) 0x39bb OR	%RDX,%RSI

  (73) 0x39be SHR	$0x1,%RSI

  (73) 0x39c1 XOR	0x1760(%RSP),%RSI

  (73) 0x39c9 MOV	%ECX,%EDX

  (73) 0x39cb AND	$0x1,%EDX

  (73) 0x39ce NEG	%EDX

  (73) 0x39d0 AND	%R8D,%EDX

  (73) 0x39d3 XOR	%RSI,%RDX

  (73) 0x39d6 MOV	%RDX,0xaf8(%RSP)

  (73) 0x39de AND	$-0x80000000,%RCX

  (73) 0x39e5 MOV	0xb08(%RSP),%RDX

  (73) 0x39ed MOV	%EDX,%ESI

  (73) 0x39ef VPBROADCASTQ	%RDX,%XMM0

  (73) 0x39f5 AND	$0x7ffffffe,%EDX

  (73) 0x39fb OR	%RCX,%RDX

  (73) 0x39fe SHR	$0x1,%RDX

  (73) 0x3a01 XOR	0x1768(%RSP),%RDX

  (73) 0x3a09 AND	$0x1,%ESI

  (73) 0x3a0c NEG	%ESI

  (73) 0x3a0e MOV	$-0x66f74f21,%EDI

  (73) 0x3a13 AND	%R8D,%ESI

  (73) 0x3a16 XOR	%RDX,%RSI

  (73) 0x3a19 MOV	%RSI,0xb00(%RSP)

  (73) 0x3a21 MOV	$0xe8,%ECX

  (73) 0x3a26 VPBROADCASTQ	0x2609(%RIP),%XMM5

  (73) 0x3a2f VPBROADCASTQ	0x2608(%RIP),%XMM6

  (73) 0x3a38 VPBROADCASTQ	0x2607(%RIP),%XMM7

  (73) 0x3a41 VPBROADCASTQ	0x2606(%RIP),%XMM8

  (73) 0x3a4a NOPW	(%RAX,%RAX,1)

    (75) 0x3a50 VMOVDQU	0x3d0(%RSP,%RCX,8),%XMM1

    (75) 0x3a59 VMOVDQU	0x3e0(%RSP,%RCX,8),%XMM2

    (75) 0x3a62 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

    (75) 0x3a68 VMOVDQU	0x3f0(%RSP,%RCX,8),%XMM3

    (75) 0x3a71 VPAND	%XMM6,%XMM1,%XMM4

    (75) 0x3a75 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM4

    (75) 0x3a7c VPSRLQ	$0x1,%XMM4,%XMM0

    (75) 0x3a81 VPXOR	-0x350(%RSP,%RCX,8),%XMM0,%XMM0

    (75) 0x3a8a VPTESTMQ	%XMM7,%XMM1,%K1

    (75) 0x3a90 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (75) 0x3a96 VMOVDQU	%XMM0,0x3c8(%RSP,%RCX,8)

    (75) 0x3a9f VPALIGNR	$0x8,%XMM1,%XMM2,%XMM0

    (75) 0x3aa5 VPAND	%XMM6,%XMM2,%XMM1

    (75) 0x3aa9 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

    (75) 0x3ab0 VPSRLQ	$0x1,%XMM1,%XMM0

    (75) 0x3ab5 VPXOR	-0x340(%RSP,%RCX,8),%XMM0,%XMM0

    (75) 0x3abe VPTESTMQ	%XMM7,%XMM2,%K1

    (75) 0x3ac4 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (75) 0x3aca VMOVDQU	%XMM0,0x3d8(%RSP,%RCX,8)

    (75) 0x3ad3 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM0

    (75) 0x3ad9 VPAND	%XMM6,%XMM3,%XMM1

    (75) 0x3add VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

    (75) 0x3ae4 VPSRLQ	$0x1,%XMM1,%XMM0

    (75) 0x3ae9 VPXOR	-0x330(%RSP,%RCX,8),%XMM0,%XMM0

    (75) 0x3af2 VPTESTMQ	%XMM7,%XMM3,%K1

    (75) 0x3af8 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (75) 0x3afe VMOVDQU	%XMM0,0x3e8(%RSP,%RCX,8)

    (75) 0x3b07 ADD	$0x6,%RCX

    (75) 0x3b0b VMOVDQA	%XMM3,%XMM0

    (75) 0x3b0f CMP	$0x274,%RCX

    (75) 0x3b16 JNE	3a50

  (73) 0x3b1c MOV	0x1768(%RSP),%RCX

  (73) 0x3b24 MOV	$-0x80000000,%RDX

  (73) 0x3b2b AND	%RDX,%RCX

  (73) 0x3b2e MOV	0x3f0(%RSP),%RDX

  (73) 0x3b36 MOV	%EDX,%ESI

  (73) 0x3b38 AND	$0x7ffffffe,%ESI

  (73) 0x3b3e OR	%RCX,%RSI

  (73) 0x3b41 SHR	$0x1,%RSI

  (73) 0x3b44 XOR	0x1050(%RSP),%RSI

  (73) 0x3b4c AND	$0x1,%EDX

  (73) 0x3b4f NEG	%EDX

  (73) 0x3b51 AND	%EDI,%EDX

  (73) 0x3b53 XOR	%RSI,%RDX

  (73) 0x3b56 MOV	%RDX,0x1768(%RSP)

  (73) 0x3b5e XOR	%ECX,%ECX

  (73) 0x3b60 JMP	3780

0x3b65 MOV	0x60(%RSP),%RDX

0x3b6a VMOVSS	%XMM0,(%RDX,%RAX,4)

0x3b6f JMP	3be3

  (70) 0x3b80 MOV	%RCX,%RDX

  (70) 0x3b83 INC	%RCX

  (70) 0x3b86 MOV	%RCX,0x1770(%RSP)

  (70) 0x3b8e MOV	0x3f0(%RSP,%RDX,8),%RDX

  (70) 0x3b96 MOV	%RDX,%RSI

  (70) 0x3b99 SHR	$0xb,%RSI

  (70) 0x3b9d MOV	%ESI,%ESI

  (70) 0x3b9f XOR	%RDX,%RSI

  (70) 0x3ba2 MOV	%ESI,%EDX

  (70) 0x3ba4 SAL	$0x7,%EDX

  (70) 0x3ba7 AND	$-0x62d3a980,%EDX

  (70) 0x3bad XOR	%RSI,%RDX

  (70) 0x3bb0 MOV	%EDX,%ESI

  (70) 0x3bb2 SAL	$0xf,%ESI

  (70) 0x3bb5 AND	$-0x103a0000,%ESI

  (70) 0x3bbb XOR	%RDX,%RSI

  (70) 0x3bbe MOV	%RSI,%RDX

  (70) 0x3bc1 SHR	$0x12,%RDX

  (70) 0x3bc5 XOR	%ESI,%EDX

  (70) 0x3bc7 VCVTUSI2SS	%EDX,%XMM15,%XMM0

  (70) 0x3bcd VMULSS	0x2433(%RIP),%XMM0,%XMM0

  (70) 0x3bd5 VUCOMISS	0x242f(%RIP),%XMM0

  (70) 0x3bdd JB	3f65

  (70) 0x3be3 CMP	$0x270,%RCX

  (70) 0x3bea JB	3b80

  (70) 0x3bec VPBROADCASTQ	0x3f0(%RSP),%ZMM0

  (70) 0x3bf4 XOR	%ECX,%ECX

  (70) 0x3bf6 VPBROADCASTQ	0x2438(%RIP),%ZMM12

  (70) 0x3c00 VPBROADCASTQ	0x2436(%RIP),%ZMM13

  (70) 0x3c0a VPBROADCASTQ	0x2434(%RIP),%ZMM14

  (70) 0x3c14 VPBROADCASTQ	0x2432(%RIP),%ZMM15

  (70) 0x3c1e XCHG	%AX,%AX

    (71) 0x3c20 VMOVDQA64	%ZMM0,%ZMM1

    (71) 0x3c26 VMOVDQU64	0x3f8(%RSP,%RCX,8),%ZMM2

    (71) 0x3c31 VMOVDQU64	0x438(%RSP,%RCX,8),%ZMM3

    (71) 0x3c3c VMOVDQU64	0x478(%RSP,%RCX,8),%ZMM4

    (71) 0x3c47 VMOVDQU64	0x4b8(%RSP,%RCX,8),%ZMM0

    (71) 0x3c52 VALIGNQ	$0x7,%ZMM1,%ZMM2,%ZMM1

    (71) 0x3c59 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM5

    (71) 0x3c60 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM6

    (71) 0x3c67 VALIGNQ	$0x7,%ZMM4,%ZMM0,%ZMM7

    (71) 0x3c6e VPANDQ	%ZMM13,%ZMM2,%ZMM8

    (71) 0x3c74 VPANDQ	%ZMM13,%ZMM3,%ZMM9

    (71) 0x3c7a VPANDQ	%ZMM13,%ZMM4,%ZMM10

    (71) 0x3c80 VPANDQ	%ZMM13,%ZMM0,%ZMM11

    (71) 0x3c86 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM1,%ZMM8

    (71) 0x3c8d VPTERNLOGQ	$-0x8,%ZMM12,%ZMM5,%ZMM9

    (71) 0x3c94 VPTERNLOGQ	$-0x8,%ZMM12,%ZMM6,%ZMM10

    (71) 0x3c9b VPTERNLOGQ	$-0x8,%ZMM12,%ZMM7,%ZMM11

    (71) 0x3ca2 VPSRLQ	$0x1,%ZMM8,%ZMM1

    (71) 0x3ca9 VPSRLQ	$0x1,%ZMM9,%ZMM5

    (71) 0x3cb0 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (71) 0x3cb7 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (71) 0x3cbe VPXORQ	0x1058(%RSP,%RCX,8),%ZMM1,%ZMM1

    (71) 0x3cc9 VPXORQ	0x1098(%RSP,%RCX,8),%ZMM5,%ZMM5

    (71) 0x3cd4 VPXORQ	0x10d8(%RSP,%RCX,8),%ZMM6,%ZMM6

    (71) 0x3cdf VPXORQ	0x1118(%RSP,%RCX,8),%ZMM7,%ZMM7

    (71) 0x3cea VPTESTMQ	%ZMM14,%ZMM2,%K1

    (71) 0x3cf0 VPTESTMQ	%ZMM14,%ZMM3,%K2

    (71) 0x3cf6 VPTESTMQ	%ZMM14,%ZMM4,%K3

    (71) 0x3cfc VPTESTMQ	%ZMM14,%ZMM0,%K4

    (71) 0x3d02 VPXORQ	%ZMM15,%ZMM1,%ZMM1{%K1}

    (71) 0x3d08 VPXORQ	%ZMM15,%ZMM5,%ZMM5{%K2}

    (71) 0x3d0e VPXORQ	%ZMM15,%ZMM6,%ZMM6{%K3}

    (71) 0x3d14 VPXORQ	%ZMM15,%ZMM7,%ZMM7{%K4}

    (71) 0x3d1a VMOVDQU64	%ZMM1,0x3f0(%RSP,%RCX,8)

    (71) 0x3d25 VMOVDQU64	%ZMM5,0x430(%RSP,%RCX,8)

    (71) 0x3d30 VMOVDQU64	%ZMM6,0x470(%RSP,%RCX,8)

    (71) 0x3d3b VMOVDQU64	%ZMM7,0x4b0(%RSP,%RCX,8)

    (71) 0x3d46 ADD	$0x20,%RCX

    (71) 0x3d4a CMP	$0xe0,%RCX

    (71) 0x3d51 JNE	3c20

  (70) 0x3d57 VEXTRACTI32X4	$0x3,%ZMM0,%XMM0

  (70) 0x3d5e VPEXTRQ	$0x1,%XMM0,%RSI

  (70) 0x3d64 AND	$-0x80000000,%RSI

  (70) 0x3d6b MOV	0xaf8(%RSP),%RDX

  (70) 0x3d73 MOV	0xb00(%RSP),%RCX

  (70) 0x3d7b MOV	%EDX,%EDI

  (70) 0x3d7d AND	$0x7ffffffe,%EDI

  (70) 0x3d83 OR	%RSI,%RDI

  (70) 0x3d86 SHR	$0x1,%RDI

  (70) 0x3d89 XOR	0x1758(%RSP),%RDI

  (70) 0x3d91 MOV	%EDX,%ESI

  (70) 0x3d93 AND	$0x1,%ESI

  (70) 0x3d96 NEG	%ESI

  (70) 0x3d98 MOV	$-0x66f74f21,%R8D

  (70) 0x3d9e AND	%R8D,%ESI

  (70) 0x3da1 XOR	%RDI,%RSI

  (70) 0x3da4 MOV	%RSI,0xaf0(%RSP)

  (70) 0x3dac AND	$-0x80000000,%RDX

  (70) 0x3db3 MOV	%ECX,%ESI

  (70) 0x3db5 AND	$0x7ffffffe,%ESI

  (70) 0x3dbb OR	%RDX,%RSI

  (70) 0x3dbe SHR	$0x1,%RSI

  (70) 0x3dc1 XOR	0x1760(%RSP),%RSI

  (70) 0x3dc9 MOV	%ECX,%EDX

  (70) 0x3dcb AND	$0x1,%EDX

  (70) 0x3dce NEG	%EDX

  (70) 0x3dd0 AND	%R8D,%EDX

  (70) 0x3dd3 XOR	%RSI,%RDX

  (70) 0x3dd6 MOV	%RDX,0xaf8(%RSP)

  (70) 0x3dde AND	$-0x80000000,%RCX

  (70) 0x3de5 MOV	0xb08(%RSP),%RDX

  (70) 0x3ded MOV	%EDX,%ESI

  (70) 0x3def VPBROADCASTQ	%RDX,%XMM0

  (70) 0x3df5 AND	$0x7ffffffe,%EDX

  (70) 0x3dfb OR	%RCX,%RDX

  (70) 0x3dfe SHR	$0x1,%RDX

  (70) 0x3e01 XOR	0x1768(%RSP),%RDX

  (70) 0x3e09 AND	$0x1,%ESI

  (70) 0x3e0c NEG	%ESI

  (70) 0x3e0e MOV	$-0x66f74f21,%EDI

  (70) 0x3e13 AND	%R8D,%ESI

  (70) 0x3e16 XOR	%RDX,%RSI

  (70) 0x3e19 MOV	%RSI,0xb00(%RSP)

  (70) 0x3e21 MOV	$0xe8,%ECX

  (70) 0x3e26 VPBROADCASTQ	0x2209(%RIP),%XMM5

  (70) 0x3e2f VPBROADCASTQ	0x2208(%RIP),%XMM6

  (70) 0x3e38 VPBROADCASTQ	0x2207(%RIP),%XMM7

  (70) 0x3e41 VPBROADCASTQ	0x2206(%RIP),%XMM8

  (70) 0x3e4a NOPW	(%RAX,%RAX,1)

    (72) 0x3e50 VMOVDQU	0x3d0(%RSP,%RCX,8),%XMM1

    (72) 0x3e59 VMOVDQU	0x3e0(%RSP,%RCX,8),%XMM2

    (72) 0x3e62 VPALIGNR	$0x8,%XMM0,%XMM1,%XMM0

    (72) 0x3e68 VMOVDQU	0x3f0(%RSP,%RCX,8),%XMM3

    (72) 0x3e71 VPAND	%XMM6,%XMM1,%XMM4

    (72) 0x3e75 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM4

    (72) 0x3e7c VPSRLQ	$0x1,%XMM4,%XMM0

    (72) 0x3e81 VPXOR	-0x350(%RSP,%RCX,8),%XMM0,%XMM0

    (72) 0x3e8a VPTESTMQ	%XMM7,%XMM1,%K1

    (72) 0x3e90 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (72) 0x3e96 VMOVDQU	%XMM0,0x3c8(%RSP,%RCX,8)

    (72) 0x3e9f VPALIGNR	$0x8,%XMM1,%XMM2,%XMM0

    (72) 0x3ea5 VPAND	%XMM6,%XMM2,%XMM1

    (72) 0x3ea9 VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

    (72) 0x3eb0 VPSRLQ	$0x1,%XMM1,%XMM0

    (72) 0x3eb5 VPXOR	-0x340(%RSP,%RCX,8),%XMM0,%XMM0

    (72) 0x3ebe VPTESTMQ	%XMM7,%XMM2,%K1

    (72) 0x3ec4 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (72) 0x3eca VMOVDQU	%XMM0,0x3d8(%RSP,%RCX,8)

    (72) 0x3ed3 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM0

    (72) 0x3ed9 VPAND	%XMM6,%XMM3,%XMM1

    (72) 0x3edd VPTERNLOGQ	$-0x8,%XMM5,%XMM0,%XMM1

    (72) 0x3ee4 VPSRLQ	$0x1,%XMM1,%XMM0

    (72) 0x3ee9 VPXOR	-0x330(%RSP,%RCX,8),%XMM0,%XMM0

    (72) 0x3ef2 VPTESTMQ	%XMM7,%XMM3,%K1

    (72) 0x3ef8 VPXORQ	%XMM8,%XMM0,%XMM0{%K1}

    (72) 0x3efe VMOVDQU	%XMM0,0x3e8(%RSP,%RCX,8)

    (72) 0x3f07 ADD	$0x6,%RCX

    (72) 0x3f0b VMOVDQA	%XMM3,%XMM0

    (72) 0x3f0f CMP	$0x274,%RCX

    (72) 0x3f16 JNE	3e50

  (70) 0x3f1c MOV	0x1768(%RSP),%RCX

  (70) 0x3f24 MOV	$-0x80000000,%RDX

  (70) 0x3f2b AND	%RDX,%RCX

  (70) 0x3f2e MOV	0x3f0(%RSP),%RDX

  (70) 0x3f36 MOV	%EDX,%ESI

  (70) 0x3f38 AND	$0x7ffffffe,%ESI

  (70) 0x3f3e OR	%RCX,%RSI

  (70) 0x3f41 SHR	$0x1,%RSI

  (70) 0x3f44 XOR	0x1050(%RSP),%RSI

  (70) 0x3f4c AND	$0x1,%EDX

  (70) 0x3f4f NEG	%EDX

  (70) 0x3f51 AND	%EDI,%EDX

  (70) 0x3f53 XOR	%RSI,%RDX

  (70) 0x3f56 MOV	%RDX,0x1768(%RSP)

  (70) 0x3f5e XOR	%ECX,%ECX

  (70) 0x3f60 JMP	3b80

0x3f65 MOV	0x98(%RSP),%RDX

0x3f6d VMOVSS	%XMM0,(%RDX,%RAX,4)

0x3f72 INC	%RAX

0x3f75 CMP	0x58(%RSP),%RAX

0x3f7a JNE	33f3

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc: 404 - 3558

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3557: 	  const _RealT __ret = _RealT(__sum >> __log2_x) / _RealT(__rd);

3558: 	  if (__ret < _RealT(1.0))

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	4.36
CQA speedup if FP arith vectorized	1.98
CQA speedup if fully vectorized	11.97
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	13.76
CQA cycles if fully vectorized	2.28
Front-end cycles	27.25
P0 cycles	16.75
P1 cycles	16.75
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	8.00
P5 cycles	16.75
P6 cycles	16.75
P7 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	107.00
Nb uops	109.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	13.00
FLOP/cycle	0.04
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.66
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.47
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	1.79
Vector-efficiency ratio all	10.02
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	10.16
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.93

Metric	Value
CQA speedup if no scalar integer	4.36
CQA speedup if FP arith vectorized	1.98
CQA speedup if fully vectorized	11.97
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:404-409,random.tcc:412-412,random.tcc:420-423,random.tcc:458-458,random.tcc:462-466,random.tcc:3557-3558,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	13.76
CQA cycles if fully vectorized	2.28
Front-end cycles	27.25
P0 cycles	16.75
P1 cycles	16.75
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	8.00
P5 cycles	16.75
P6 cycles	16.75
P7 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	107.00
Nb uops	109.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	13.00
FLOP/cycle	0.04
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.66
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.47
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	1.79
Vector-efficiency ratio all	10.02
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	10.16
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-skl512

The loop is defined in:

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.25 to 6.25 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 27.25 to 2.28 cycles (11.97x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VPEXTRQ: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404
VUCOMISS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3558

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 184 bytes (46 single precision FP elements). The binary loop is storing 52 bytes (13 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	107
nb uops	109
loop length	528
used x86 registers	8
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	5
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.25 cycles
front end	27.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	16.75	16.75	12.00	12.00	8.00	16.75	16.75	8.00
cycles	16.75	16.75	12.00	12.00	8.00	16.75	16.75	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.25
Dispatch	16.75
Overall L1	27.25

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	11%
store	10%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.25 cycles. At this rate:

5% of peak load performance is reached (6.75 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.25 to 16.75 cycles (1.63x speedup).

ASM code

In the binary file, the address of the loop is: 33f3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RCX,0x1770(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x3f0(%RSP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR %ESI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x2c23(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS 0x2c1f(%RIP),%XMM0	2	1	0	0.50	0.50	0	0	0	0	3	1	scal (6.3%)
JB 3775 <main+0x11d5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 3390 <main+0xdf0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0x3f0(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ 0x2c28(%RIP),%ZMM12	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c26(%RIP),%ZMM13	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c24(%RIP),%ZMM14	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c22(%RIP),%ZMM15	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTI32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPEXTRQ $0x1,%XMM0,%RSI	2	1	0	0	0	0	1	0	0	3	1	scal (12.5%)
AND $-0x80000000,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xaf8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xb00(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1758(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xaf0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1760(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %R8D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0xaf8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb08(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
AND $0x7ffffffe,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
OR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR 0x1768(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xb00(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0xe8,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VPBROADCASTQ 0x29f9(%RIP),%XMM5	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f8(%RIP),%XMM6	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f7(%RIP),%XMM7	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f6(%RIP),%XMM8	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1768(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RDX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RCX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1050(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %EDI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0x1768(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 3390 <main+0xdf0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%RBX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 37e3 <main+0x1243>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x60(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 3be3 <main+0x1643>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x58(%RSP),%RAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 33f3 <main+0xe53>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-skl512

The loop is defined in:

/usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404-423,458-466,3557-3558
/home/eoseret/Applications/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.25 to 6.25 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557
VPEXTRQ: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:404
VUCOMISS: 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3558

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/16.1.1/../../../../include/c++/16.1.1/bits/random.tcc:3557

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 184 bytes (46 single precision FP elements). The binary loop is storing 52 bytes (13 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	107
nb uops	109
loop length	528
used x86 registers	8
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	5
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.25 cycles
front end	27.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	16.75	16.75	12.00	12.00	8.00	16.75	16.75	8.00
cycles	16.75	16.75	12.00	12.00	8.00	16.75	16.75	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.25
Dispatch	16.75
Overall L1	27.25

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

INT+FP

all	10%
load	11%
store	10%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.25 cycles. At this rate:

5% of peak load performance is reached (6.75 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.91 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 33f3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
INC %RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RCX,0x1770(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV 0x3f0(%RSP,%RDX,8),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR %ESI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
VCVTUSI2SS %EDX,%XMM15,%XMM0	2	0.50	0.50	0	0	0	1	0	0	6	1	scal (6.3%)
VMULSS 0x2c23(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VUCOMISS 0x2c1f(%RIP),%XMM0	2	1	0	0.50	0.50	0	0	0	0	3	1	scal (6.3%)
JB 3775 <main+0x11d5>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMP $0x270,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
JB 3390 <main+0xdf0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VPBROADCASTQ 0x3f0(%RSP),%ZMM0	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ 0x2c28(%RIP),%ZMM12	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c26(%RIP),%ZMM13	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c24(%RIP),%ZMM14	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VPBROADCASTQ 0x2c22(%RIP),%ZMM15	1	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
VEXTRACTI32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	3	1	vect (25.0%)
VPEXTRQ $0x1,%XMM0,%RSI	2	1	0	0	0	0	1	0	0	3	1	scal (12.5%)
AND $-0x80000000,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xaf8(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV 0xb00(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RSI,%RDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1758(%RSP),%RDI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDI,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xaf0(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1760(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.25	N/A
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %R8D,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0xaf8(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
AND $-0x80000000,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0xb08(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VPBROADCASTQ %RDX,%XMM0	1	0	0	0	0	0	1	0	0	1	1	scal (12.5%)
AND $0x7ffffffe,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
OR %RCX,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	1	0.50	N/A
XOR 0x1768(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
AND $0x1,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
NEG %ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
MOV $-0x66f74f21,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
AND %R8D,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
XOR %RDX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV %RSI,0xb00(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
MOV $0xe8,%ECX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
VPBROADCASTQ 0x29f9(%RIP),%XMM5	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f8(%RIP),%XMM6	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f7(%RIP),%XMM7	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ 0x29f6(%RIP),%XMM8	1	0	0	0.50	0.50	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1768(%RSP),%RCX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %RDX,%RCX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (6.3%)
OR %RCX,%RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	1	0.50	scal (12.5%)
XOR 0x1050(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
AND $0x1,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
NEG %EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
AND %EDI,%EDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
XOR %RSI,%RDX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV %RDX,0x1768(%RSP)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 3390 <main+0xdf0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
VMOVSS %XMM0,(%RBX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 37e3 <main+0x1243>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x60(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
JMP 3be3 <main+0x1643>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%RDX,%RAX,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RAX	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x58(%RSP),%RAX	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JNE 33f3 <main+0xe53>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code