OV - attention-clang-skl512 - Loop 67 - attention-clang-skl512

	Loop Id: 67	Module: attention-clang-skl512	Source: attention_v2.cpp:27-33	Coverage: 0.43%

0x3fd0 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x3fd4 LEA	(%RDX,%RSI,1),%EDI

0x3fd7 MOV	0x20(%RSP),%R8

0x3fdc VMOVSS	%XMM0,(%R8,%RDI,4)

0x3fe2 INC	%RSI

0x3fe5 CMP	0x30(%RSP),%RSI

0x3fea JE	3fa0

0x3fec CMPL	$0x3,0xd8(%RSP)

0x3ff4 JAE	4010

0x3ff6 VXORPS	%XMM0,%XMM0,%XMM0

0x3ffa XOR	%EDI,%EDI

0x3ffc JMP	40d5

0x4010 VXORPS	%XMM0,%XMM0,%XMM0

0x4014 MOV	%RSI,%R8

0x4017 XOR	%EDI,%EDI

0x4019 MOV	0xc8(%RSP),%R10

0x4021 LEA	(%R12,%R12,2),%R11

0x4025 LEA	(%R12,%R12,1),%RAX

0x4029 NOPL	(%RAX)

  (31) 0x4030 LEA	(%RCX,%RDI,1),%R9D

  (31) 0x4034 VMOVSS	(%R14,%R9,4),%XMM1

  (31) 0x403a VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (31) 0x403e MOV	%R8D,%R9D

  (31) 0x4041 VMOVSS	(%RBX,%R9,4),%XMM2

  (31) 0x4047 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (31) 0x404b LEA	0x1(%RCX,%RDI,1),%R9D

  (31) 0x4050 VMOVSS	(%R14,%R9,4),%XMM3

  (31) 0x4056 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (31) 0x405a LEA	(%R12,%R8,1),%R9D

  (31) 0x405e VMOVSS	(%RBX,%R9,4),%XMM4

  (31) 0x4064 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (31) 0x4068 LEA	0x2(%RCX,%RDI,1),%R9D

  (31) 0x406d VMOVSS	(%R14,%R9,4),%XMM5

  (31) 0x4073 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (31) 0x4078 VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (31) 0x407c LEA	(%RAX,%R8,1),%R9D

  (31) 0x4080 VMOVSS	(%RBX,%R9,4),%XMM1

  (31) 0x4086 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (31) 0x408b VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (31) 0x408f LEA	0x3(%RCX,%RDI,1),%R9D

  (31) 0x4094 VMOVSS	(%R14,%R9,4),%XMM2

  (31) 0x409a VFMADD213SD	%XMM4,%XMM0,%XMM1

  (31) 0x409f VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (31) 0x40a3 LEA	(%R11,%R8,1),%R9D

  (31) 0x40a7 VMOVSS	(%RBX,%R9,4),%XMM0

  (31) 0x40ad VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (31) 0x40b1 VFMADD213SD	%XMM1,%XMM2,%XMM0

  (31) 0x40b6 ADD	$0x4,%RDI

  (31) 0x40ba ADD	%R13,%R8

  (31) 0x40bd CMP	%RDI,%R10

  (31) 0x40c0 JNE	4030

0x40c6 CMPQ	$0,0xd0(%RSP)

0x40cf JE	3fd0

0x40d5 MOV	%R12,%R8

0x40d8 IMUL	%RDI,%R8

0x40dc ADD	%RSI,%R8

0x40df ADD	%ECX,%EDI

0x40e1 MOV	0xd0(%RSP),%R9

0x40e9 NOPL	(%RAX)

  (68) 0x40f0 MOV	%EDI,%R10D

  (68) 0x40f3 VMOVSS	(%R14,%R10,4),%XMM1

  (68) 0x40f9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (68) 0x40fd MOV	%R8D,%R10D

  (68) 0x4100 VMOVSS	(%RBX,%R10,4),%XMM2

  (68) 0x4106 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (68) 0x410a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (68) 0x410f ADD	%R12,%R8

  (68) 0x4112 INC	%EDI

  (68) 0x4114 DEC	%R9

  (68) 0x4117 JNE	40f0

0x4119 JMP	3fd0

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.41
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.42
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	0.40
Front-end cycles	5.42
P0 cycles	3.42
P1 cycles	3.42
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	1.00
P5 cycles	3.42
P6 cycles	3.42
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.67
Nb uops	21.67
Nb loads	5.00
Nb stores	1.00
Nb stack references	4.67
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.40
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.67
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	15.28
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	23.33
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.69
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.96

Metric	Value
CQA speedup if no scalar integer	2.22
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.36
Front-end cycles	5.00
P0 cycles	3.25
P1 cycles	3.25
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	20.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.06

Metric	Value
CQA speedup if no scalar integer	2.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.49
Front-end cycles	6.50
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	1.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	26.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.38
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	12.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	11.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.75

Metric	Value
CQA speedup if no scalar integer	2.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	0.35
Front-end cycles	4.75
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	1.00
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	19.00
Nb loads	5.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.42
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.06

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.42 to 0.40 cycles (13.59x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20.67
nb uops	21.67
loop length	94.33
used x86 registers	9.67
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4.67

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	5.42 cycles
front end	5.42 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.42	3.42	2.50	2.50	1.00	3.42	3.42	1.00
cycles	3.42	3.42	2.50	2.50	1.00	3.42	3.42	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.42
Dispatch	3.42
Data deps.	0.00
Overall L1	5.42

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	15%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.42 cycles. At this rate:

5% of peak load performance is reached (6.65 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.75 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 2.25 cycles (2.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	19
nb uops	20
loop length	81
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.25	3.25	2.00	2.00	1.00	3.25	3.25	1.00
cycles	3.25	3.25	2.00	2.00	1.00	3.25	3.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.00
Dispatch	3.25
Data deps.	0.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

4% of peak load performance is reached (5.60 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.25 cycles (1.54x speedup).

ASM code

In the binary file, the address of the loop is: 3fec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x20(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 3fa0 <main+0x1a00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4010 <main+0x1a70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40d5 <main+0x1b35>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 3fd0 <main+0x1a30>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 2.50 cycles (2.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 44 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	25
nb uops	26
loop length	117
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	3.00	3.00	1.00	4.00	4.00	1.00
cycles	4.00	4.00	3.00	3.00	1.00	4.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.50
Dispatch	4.00
Data deps.	0.00
Overall L1	6.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

5% of peak load performance is reached (6.77 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.62 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 3fec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x20(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 3fa0 <main+0x1a00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4010 <main+0x1a70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
LEA (%R12,%R12,2),%R11	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMPQ $0,0xd0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 3fd0 <main+0x1a30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	N/A
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 3fd0 <main+0x1a30>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.75 to 2.00 cycles (2.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	18
nb uops	19
loop length	85
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.00	3.00	2.50	2.50	1.00	3.00	3.00	1.00
cycles	3.00	3.00	2.50	2.50	1.00	3.00	3.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	3.00
Data deps.	0.00
Overall L1	4.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

5% of peak load performance is reached (7.58 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 3fec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
MOV 0x20(%RSP),%R8	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	N/A
VMOVSS %XMM0,(%R8,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 3fa0 <main+0x1a00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 4010 <main+0x1a70>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
LEA (%R12,%R12,2),%R11	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
CMPQ $0,0xd0(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	N/A
JE 3fd0 <main+0x1a30>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access