OV - attention-clang-skl512 - Loop 61 - attention-clang-skl512

	Loop Id: 61	Module: attention-clang-skl512	Source: attention_v2.cpp:27-33	Coverage: 0.38%

0x4370 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x4374 LEA	(%RDX,%RSI,1),%EDI

0x4377 VMOVSS	%XMM0,(%R15,%RDI,4)

0x437d INC	%RSI

0x4380 CMP	0x30(%RSP),%RSI

0x4385 JE	4340

0x4387 CMPL	$0x3,0xd8(%RSP)

0x438f JAE	43a0

0x4391 VXORPS	%XMM0,%XMM0,%XMM0

0x4395 XOR	%EDI,%EDI

0x4397 JMP	4460

0x43a0 VXORPS	%XMM0,%XMM0,%XMM0

0x43a4 MOV	%RSI,%R8

0x43a7 XOR	%EDI,%EDI

0x43a9 MOV	0xc8(%RSP),%R10

0x43b1 LEA	(%R12,%R12,2),%R11

0x43b5 LEA	(%R12,%R12,1),%RAX

0x43b9 NOPL	(%RAX)

  (33) 0x43c0 LEA	(%RCX,%RDI,1),%R9D

  (33) 0x43c4 VMOVSS	(%R14,%R9,4),%XMM1

  (33) 0x43ca VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (33) 0x43ce MOV	%R8D,%R9D

  (33) 0x43d1 VMOVSS	(%RBX,%R9,4),%XMM2

  (33) 0x43d7 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (33) 0x43db LEA	0x1(%RCX,%RDI,1),%R9D

  (33) 0x43e0 VMOVSS	(%R14,%R9,4),%XMM3

  (33) 0x43e6 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (33) 0x43ea LEA	(%R12,%R8,1),%R9D

  (33) 0x43ee VMOVSS	(%RBX,%R9,4),%XMM4

  (33) 0x43f4 VCVTSS2SD	%XMM4,%XMM4,%XMM4

  (33) 0x43f8 LEA	0x2(%RCX,%RDI,1),%R9D

  (33) 0x43fd VMOVSS	(%R14,%R9,4),%XMM5

  (33) 0x4403 VFMADD213SD	%XMM0,%XMM1,%XMM2

  (33) 0x4408 VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (33) 0x440c LEA	(%RAX,%R8,1),%R9D

  (33) 0x4410 VMOVSS	(%RBX,%R9,4),%XMM1

  (33) 0x4416 VFMADD213SD	%XMM2,%XMM3,%XMM4

  (33) 0x441b VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (33) 0x441f LEA	0x3(%RCX,%RDI,1),%R9D

  (33) 0x4424 VMOVSS	(%R14,%R9,4),%XMM2

  (33) 0x442a VFMADD213SD	%XMM4,%XMM0,%XMM1

  (33) 0x442f VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (33) 0x4433 LEA	(%R11,%R8,1),%R9D

  (33) 0x4437 VMOVSS	(%RBX,%R9,4),%XMM0

  (33) 0x443d VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (33) 0x4441 VFMADD213SD	%XMM1,%XMM2,%XMM0

  (33) 0x4446 ADD	$0x4,%RDI

  (33) 0x444a ADD	%R13,%R8

  (33) 0x444d CMP	%RDI,%R10

  (33) 0x4450 JNE	43c0

0x4456 TEST	$0x3,%R12B

0x445a JE	4370

0x4460 MOV	%R12,%R8

0x4463 IMUL	%RDI,%R8

0x4467 ADD	%RSI,%R8

0x446a ADD	%ECX,%EDI

0x446c MOV	0xd0(%RSP),%R9

0x4474 NOPW	%CS:(%RAX,%RAX,1)

  (62) 0x4480 MOV	%EDI,%R10D

  (62) 0x4483 VMOVSS	(%R14,%R10,4),%XMM1

  (62) 0x4489 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (62) 0x448d MOV	%R8D,%R10D

  (62) 0x4490 VMOVSS	(%RBX,%R10,4),%XMM2

  (62) 0x4496 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (62) 0x449a VFMADD231SD	%XMM2,%XMM1,%XMM0

  (62) 0x449f ADD	%R12,%R8

  (62) 0x44a2 INC	%EDI

  (62) 0x44a4 DEC	%R9

  (62) 0x44a7 JNE	4480

0x44a9 JMP	4370

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.26
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.08
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	5.08
CQA cycles if fully vectorized	0.39
Front-end cycles	5.08
P0 cycles	3.33
P1 cycles	3.33
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.00
P5 cycles	3.33
P6 cycles	3.33
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.67
Nb uops	20.33
Nb loads	3.33
Nb stores	1.00
Nb stack references	3.33
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.27
Bytes prefetched	0.00
Bytes loaded	22.67
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.67
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	11.50
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.89
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.59
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.68

Metric	Value
CQA speedup if no scalar integer	2.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	0.38
Front-end cycles	4.75
P0 cycles	3.25
P1 cycles	3.25
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.00
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	19.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.05
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.75

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.56
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	0.49
Front-end cycles	6.25
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.00
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	25.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.12
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	9.09
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.94
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.54

Metric	Value
CQA speedup if no scalar integer	2.13
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.55
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.25
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	0.31
Front-end cycles	4.25
P0 cycles	2.75
P1 cycles	2.75
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.00
P5 cycles	2.75
P6 cycles	2.75
P7 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.65
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	10.42
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:27,30,33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.08 to 0.39 cycles (12.92x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 22 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	19.67
nb uops	20.33
loop length	89.33
used x86 registers	10.67
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	5.08 cycles
front end	5.08 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.33	3.33	1.67	1.67	1.00	3.33	3.33	1.00
cycles	3.33	3.33	1.67	1.67	1.00	3.33	3.33	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.08
Dispatch	3.33
Data deps.	0.00
Overall L1	5.08

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.08 cycles. At this rate:

3% of peak load performance is reached (4.47 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.81 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.75 to 2.25 cycles (2.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	18
nb uops	19
loop length	81
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	3.25	3.25	1.50	1.50	1.00	3.25	3.25	1.00
cycles	3.25	3.25	1.50	1.50	1.00	3.25	3.25	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.75
Dispatch	3.25
Data deps.	0.00
Overall L1	4.75

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

3% of peak load performance is reached (4.21 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.75 to 3.25 cycles (1.46x speedup).

ASM code

In the binary file, the address of the loop is: 4387

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%R15,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4340 <main+0x1da0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 43a0 <main+0x1e00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4460 <main+0x1ec0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4370 <main+0x1dd0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.25 to 2.50 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	24
nb uops	25
loop length	112
used x86 registers	12
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	4.00	4.00	2.00	2.00	1.00	4.00	4.00	1.00
cycles	4.00	4.00	2.00	2.00	1.00	4.00	4.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	6.25
Dispatch	4.00
Data deps.	0.00
Overall L1	6.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	9%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	11%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

3% of peak load performance is reached (4.48 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.64 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4387

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%R15,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4340 <main+0x1da0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 43a0 <main+0x1e00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
LEA (%R12,%R12,2),%R11	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4370 <main+0x1dd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RSI,%R8	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	scal (12.5%)
ADD %ECX,%EDI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
MOV 0xd0(%RSP),%R9	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4370 <main+0x1dd0>	1	0	0	0	0	0	0	1	0	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-skl512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.25 to 2.00 cycles (2.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/Applications/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	17
nb uops	17
loop length	75
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.25 cycles
front end	4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	2.75	2.75	1.50	1.50	1.00	2.75	2.75	1.00
cycles	2.75	2.75	1.50	1.50	1.00	2.75	2.75	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.25
Dispatch	2.75
Data deps.	0.00
Overall L1	4.25

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	14%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

3% of peak load performance is reached (4.71 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.94 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4387

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
VMOVSS %XMM0,(%R15,%RDI,4)	1	0	0	0.33	0.33	1	0	0	0.33	3	1	scal (6.3%)
INC %RSI	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
CMP 0x30(%RSP),%RSI	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (12.5%)
JE 4340 <main+0x1da0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
CMPL $0x3,0xd8(%RSP)	1	0.25	0.25	0.50	0.50	0	0.25	0.25	0	1	0.50	scal (6.3%)
JAE 43a0 <main+0x1e00>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0.25	scal (12.5%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	0	0	4-5	0.50	scal (12.5%)
LEA (%R12,%R12,2),%R11	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
LEA (%R12,%R12,1),%RAX	1	0	0.50	0	0	0	0.50	0	0	1	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.25	N/A
TEST $0x3,%R12B	1	0.25	0.25	0	0	0	0.25	0.25	0	1	0.25	N/A
JE 4370 <main+0x1dd0>	1	0.50	0	0	0	0	0	0.50	0	0	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access