OV - attention-clang-skl512 - Loop 57 - attention-clang-skl512

	Loop Id: 57	Module: attention-clang-skl512	Source: attention_v2.cpp:236-238	Coverage: 0.02%

0x4500 INC	%RDX

0x4503 ADD	0x230(%RSP),%RCX

0x450b ADD	$0x4,%RAX

0x450f CMP	0x238(%RSP),%RDX

0x4517 JE	4690

0x451d MOV	0x30(%RSP),%R9

0x4522 CMP	$0x4,%R9D

0x4526 JAE	4540

0x4528 XOR	%EDI,%EDI

0x452a MOV	0xb8(%RSP),%R10

0x4532 JMP	465d

0x4540 LEA	(%RBX,%RDX,4),%RSI

0x4544 CMP	$0x10,%R9D

0x4548 JAE	4560

0x454a XOR	%R8D,%R8D

0x454d JMP	45f9

0x4560 XOR	%EDI,%EDI

0x4562 VMOVDQA64	0x1b54(%RIP),%ZMM0

0x456c VMOVDQA64	0x1b0a(%RIP),%ZMM1

0x4576 MOV	0x1e0(%RSP),%R8

0x457e VMOVDQA64	0x380(%RSP),%ZMM5

0x4586 VPBROADCASTQ	0x1ac8(%RIP),%ZMM6

  (34) 0x4590 VPMULLQ	%ZMM5,%ZMM0,%ZMM2

  (34) 0x4596 VMOVUPS	(%RCX,%RDI,4),%YMM3

  (34) 0x459b VMOVUPS	0x20(%RCX,%RDI,4),%YMM4

  (34) 0x45a1 KXNORB	%K0,%K0,%K1

  (34) 0x45a5 VSCATTERQPS	%YMM3,(%RSI,%ZMM2,4){%K1}

  (34) 0x45ac VPMULLQ	%ZMM5,%ZMM1,%ZMM2

  (34) 0x45b2 KXNORB	%K0,%K0,%K1

  (34) 0x45b6 VSCATTERQPS	%YMM4,(%RSI,%ZMM2,4){%K1}

  (34) 0x45bd ADD	$0x10,%RDI

  (34) 0x45c1 VPADDQ	%ZMM6,%ZMM0,%ZMM0

  (34) 0x45c7 VPADDQ	%ZMM6,%ZMM1,%ZMM1

  (34) 0x45cd CMP	%RDI,%R8

  (34) 0x45d0 JNE	4590

0x45d2 MOV	0x30(%RSP),%R9

0x45d7 CMP	%R8D,%R9D

0x45da MOV	0xb8(%RSP),%R10

0x45e2 JE	4500

0x45e8 MOV	0x1e0(%RSP),%RDI

0x45f0 MOV	%RDI,%R8

0x45f3 TEST	$0xc,%R12B

0x45f7 JE	465d

0x45f9 VPBROADCASTQ	%R8,%YMM0

0x45ff VPOR	0x1af9(%RIP),%YMM0,%YMM0

0x4607 MOV	0xc8(%RSP),%R10

0x460f VMOVDQA64	0x380(%RSP),%ZMM3

0x4617 VPBROADCASTQ	0x1a40(%RIP),%YMM4

  (59) 0x4620 VMOVUPS	(%RCX,%R8,4),%XMM1

  (59) 0x4626 VPMULLQ	%YMM3,%YMM0,%YMM2

  (59) 0x462c KXNORW	%K0,%K0,%K1

  (59) 0x4630 VSCATTERQPS	%XMM1,(%RSI,%YMM2,4){%K1}

  (59) 0x4637 ADD	$0x4,%R8

  (59) 0x463b VPADDQ	%YMM4,%YMM0,%YMM0

  (59) 0x463f CMP	%R8,%R10

  (59) 0x4642 JNE	4620

0x4644 MOV	%R10,%RDI

0x4647 MOV	0x30(%RSP),%R9

0x464c CMP	%R10D,%R9D

0x464f MOV	0xb8(%RSP),%R10

0x4657 JE	4500

0x465d MOV	%R10,%RSI

0x4660 IMUL	%RDI,%RSI

0x4664 ADD	%RAX,%RSI

0x4667 NOPW	(%RAX,%RAX,1)

  (58) 0x4670 VMOVD	(%RCX,%RDI,4),%XMM0

  (58) 0x4675 VMOVD	%XMM0,(%RSI)

  (58) 0x4679 INC	%RDI

  (58) 0x467c ADD	%R10,%RSI

  (58) 0x467f CMP	%RDI,%R9

  (58) 0x4682 JNE	4670

0x4684 JMP	4500

/home/eoseret/Applications/llm-attention/attention_v2.cpp: 236 - 238

--------------------------------------------------------------------------------

236:       for (int i = 0; i < context_size; ++i)

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_init_first	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-clang-skl512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.37
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.25
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	11.25
CQA cycles if fully vectorized	7.13
Front-end cycles	11.25
P0 cycles	5.75
P1 cycles	5.67
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	0.00
P5 cycles	5.83
P6 cycles	5.75
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.84
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	17.86
Vectorization ratio load	27.78
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.14
Vector-efficiency ratio all	24.78
Vector-efficiency ratio load	34.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.05

Metric	Value
CQA speedup if no scalar integer	2.37
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:236-237
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.25
CQA cycles if no scalar integer	4.75
CQA cycles if FP arith vectorized	11.25
CQA cycles if fully vectorized	7.13
Front-end cycles	11.25
P0 cycles	5.75
P1 cycles	5.67
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	0.00
P5 cycles	5.83
P6 cycles	5.75
P7 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.84
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	17.86
Vectorization ratio load	27.78
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	7.14
Vector-efficiency ratio all	24.78
Vector-efficiency ratio load	34.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.05

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:236-238
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:236-238.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:236-237.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 4.75 cycles (2.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.25 to 7.12 cycles (1.58x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 392 bytes.

General properties

nb instructions	45
nb uops	45
loop length	248
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	5
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.75	5.67	9.00	9.00	0.00	5.83	5.75	0.00
cycles	5.75	5.67	9.00	9.00	0.00	5.83	5.75	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Dispatch	9.00
Overall L1	11.25

Vectorization ratios

all	17%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	24%
load	34%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.25 cycles. At this rate:

27% of peak load performance is reached (34.84 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.25 to 9.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 451d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD 0x230(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
ADD $0x4,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP 0x238(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
JE 4690 <main+0x20f0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP $0x4,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 4540 <main+0x1fa0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JMP 465d <main+0x20bd>	1	0	0	0	0	0	1	0	1-2	N/A
LEA (%RBX,%RDX,4),%RSI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
CMP $0x10,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 4560 <main+0x1fc0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 45f9 <main+0x2059>	1	0	0	0	0	0	1	0	1-2	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA64 0x1b54(%RIP),%ZMM0	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVDQA64 0x1b0a(%RIP),%ZMM1	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
MOV 0x1e0(%RSP),%R8	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
VMOVDQA64 0x380(%RSP),%ZMM5	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPBROADCASTQ 0x1ac8(%RIP),%ZMM6	1	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R8D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x1f60>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x1e0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 465d <main+0x20bd>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VPBROADCASTQ %R8,%YMM0	1	0	0	0	0	1	0	1	1	scal (12.5%)
VPOR 0x1af9(%RIP),%YMM0,%YMM0	1	0.33	0.33	0.50	0.50	0.33	0	1	0.50	vect (50.0%)
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
VMOVDQA64 0x380(%RSP),%ZMM3	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPBROADCASTQ 0x1a40(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R10D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x1f60>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 4500 <main+0x1f60>	1	0	0	0	0	0	1	0	1-2	N/A

Function	main
Source file and lines	attention_v2.cpp:236-238
Module	attention-clang-skl512

The loop is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:236-238.

Analyzed code is defined in /home/eoseret/Applications/llm-attention/attention_v2.cpp:236-237.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.25 to 4.75 cycles (2.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 392 bytes.

General properties

nb instructions	45
nb uops	45
loop length	248
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	5
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.25 cycles
front end	11.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	5.75	5.67	9.00	9.00	0.00	5.83	5.75	0.00
cycles	5.75	5.67	9.00	9.00	0.00	5.83	5.75	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): store address, load
P3 (512 bits): store address, load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.25
Dispatch	9.00
Overall L1	11.25

Vectorization ratios

all	17%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

all	24%
load	34%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.25 cycles. At this rate:

27% of peak load performance is reached (34.84 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 451d

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
ADD 0x230(%RSP),%RCX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
ADD $0x4,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
CMP 0x238(%RSP),%RDX	1	0.25	0.25	0.50	0.50	0.25	0.25	1	0.50	scal (12.5%)
JE 4690 <main+0x20f0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP $0x4,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 4540 <main+0x1fa0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JMP 465d <main+0x20bd>	1	0	0	0	0	0	1	0	1-2	N/A
LEA (%RBX,%RDX,4),%RSI	1	0	0.50	0	0	0.50	0	1	0.50	N/A
CMP $0x10,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
JAE 4560 <main+0x1fc0>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 45f9 <main+0x2059>	1	0	0	0	0	0	1	0	1-2	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVDQA64 0x1b54(%RIP),%ZMM0	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVDQA64 0x1b0a(%RIP),%ZMM1	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
MOV 0x1e0(%RSP),%R8	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
VMOVDQA64 0x380(%RSP),%ZMM5	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPBROADCASTQ 0x1ac8(%RIP),%ZMM6	1	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R8D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x1f60>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV 0x1e0(%RSP),%RDI	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
TEST $0xc,%R12B	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
JE 465d <main+0x20bd>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
VPBROADCASTQ %R8,%YMM0	1	0	0	0	0	1	0	1	1	scal (12.5%)
VPOR 0x1af9(%RIP),%YMM0,%YMM0	1	0.33	0.33	0.50	0.50	0.33	0	1	0.50	vect (50.0%)
MOV 0xc8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
VMOVDQA64 0x380(%RSP),%ZMM3	1	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPBROADCASTQ 0x1a40(%RIP),%YMM4	1	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0.25	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
CMP %R10D,%R9D	1	0.25	0.25	0	0	0.25	0.25	1	0.25	scal (6.3%)
MOV 0xb8(%RSP),%R10	1	0	0	0.50	0.50	0	0	4-5	0.50	scal (12.5%)
JE 4500 <main+0x1f60>	1	0.50	0	0	0	0	0.50	0	0.50-1	N/A
MOV %R10,%RSI	1	0	0	0	0	0	0	0	0.25	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	3	1	N/A
ADD %RAX,%RSI	1	0.25	0.25	0	0	0.25	0.25	1	0.25	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0.25	N/A
JMP 4500 <main+0x1f60>	1	0	0	0	0	0	1	0	1-2	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code